mirror of https://github.com/lnis-uofu/SOFA.git
32 lines
772 B
Coq
32 lines
772 B
Coq
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//-------------------------------------------------------------------
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// Function: Testbench for the Binary to Decimal converter
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// Source:
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// https://verilogcodes.blogspot.com/2015/10/verilog-code-for-8-bit-binary-to-bcd.html
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module tb_bin2bcd;
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// Input
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reg [7:0] bin;
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// Output
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wire [11:0] bcd;
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// Extra variables
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reg [8:0] i;
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// Instantiate the Unit Under Test (UUT)
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bin2bcd uut (
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.bin(bin),
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.bcd(bcd)
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);
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//Simulation - Apply inputs
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initial begin
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//A for loop for checking all the input combinations.
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for(i=0;i<256;i=i+1)
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begin
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bin = i;
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#10; //wait for 10 ns.
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end
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$finish; //system function for stoping the simulation.
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end
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endmodule
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