2020-10-27 00:59:20 -05:00
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FPGA22_HIER_SKY_PNR
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====================
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2020-10-27 16:51:16 -05:00
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2x2 FPGA designed using hierarchical flow and `SKY130_FD_SC_HD`.
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Utilization set to 60%
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2020-10-27 00:59:20 -05:00
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Directory Structure
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-------------------
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2020-10-27 15:54:19 -05:00
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- **FPGA22_HIER_SKY_task** :- OpenFPGA task directory and all related files
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- **FPGA22_HIER_SKY_Verilog** :- Verilog-netlist used for this design
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- **modules** :- Final files of each module (lef,def,spef,v,gds)
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- **fpga_core** :- Final files of fpga_core (eFPGA design)
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- **fpga_top** :- Reserved for design with GPIOs or caravel
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2020-10-27 00:59:20 -05:00
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Checks
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---------
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- .tech file DRC - Clean
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- Timing SignOff - Clean
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Pending
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---------
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- DRC SignOff
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2020-10-27 15:54:19 -05:00
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- LVS SignOff
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2020-10-27 00:59:20 -05:00
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- PostPnR function simulation
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