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SOFA/FPGA22_HIER_SKY_PNR
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Ganesh Gore 934abfac9b Added SPEF files in git lfs 2020-10-28 12:39:15 -06:00
..
FPGA22_HIER_SKY_Verilog [DESIGN] Updated FPGA22 Design 2020-10-27 14:54:19 -06:00
FPGA22_HIER_SKY_task dropped symbolic link 2020-10-27 11:21:20 -06:00
fpga_core Added SPEF files in git lfs 2020-10-28 12:39:15 -06:00
modules Added SPEF files in git lfs 2020-10-28 12:39:15 -06:00
README.md [UPDATE] Updated reports and screenshots 2020-10-27 15:51:16 -06:00

README.md

FPGA22_HIER_SKY_PNR

2x2 FPGA designed using hierarchical flow and SKY130_FD_SC_HD. Utilization set to 60%

Directory Structure

  • FPGA22_HIER_SKY_task :- OpenFPGA task directory and all related files
  • FPGA22_HIER_SKY_Verilog :- Verilog-netlist used for this design
  • modules :- Final files of each module (lef,def,spef,v,gds)
  • fpga_core :- Final files of fpga_core (eFPGA design)
  • fpga_top :- Reserved for design with GPIOs or caravel

Checks

  • .tech file DRC - Clean
  • Timing SignOff - Clean

Pending

  • DRC SignOff
  • LVS SignOff
  • PostPnR function simulation