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# SOFA
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## Introduction
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SOFA (**S**kywater **O**pensource **F**PG**A**s) are a series of open-source FPGA IPs using the open-source [Skywater 130nm PDK ](https://github.com/google/skywater-pdk ) and [OpenFPGA ](https://github.com/lnis-uofu/OpenFPGA ) framework
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< p >
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< img src = "./DOC/source/device/hd_fpga/figures/sofa_hd_layout.png" width = "200" align = "right" >
< img src = "./DOC/source/device/hd_fpga/figures/qlsofa_hd_layout.png" width = "200" align = "right" >
< img src = "./DOC/source/device/hd_fpga/figures/sofa_chd_layout.png" width = "200" align = "right" >
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< / p >
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## Quick Start
```bash
#Clone the repository and go inside it
git clone https://github.com/LNIS-Projects/skywater-openfpga.git
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python3 SCRIPT/repo_setup.py --openfpga_root_path ${OPENFPGA_PROJECT_DIRECTORY}
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```
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---
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* If you have openfpga repository cloned at the same level of this project, you can simple call
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```bash
python3 SCRIPT/repo_setup.py
```
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Otherwise, you should provide full path using the option _--openfpga\_root\_path_
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## Chip Gallery
You can find a chip gallery in the online documentation.
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## Directory Organization
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* Keep this folder clean and organized as follows
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- **DOC**: documentation of the project
- **ARCH**: Architecture XML and other input files which OpenFPGA requires to generate Verilog netlists
- **BENCHMARK**: Benchmarks to be tested on the FPGA fabric
- **HDL**: Hardware description netlists for the FPGA fabrics
- **SDC**: design constraints
- **SCRIPT**: Scripts to setup, run OpenFPGA etc.
- **TESTBENCH**: Verilog testbenches generated by OpenFPGA
- **PDK**: Technology files linked from skywater opensource pdk
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- **SNPS\_ICC2**: workspace of Synopsys IC Compiler 2
Keep a README inside the folder about the ICC2 version and how-to-use.
- **MSIM**: workspace of verification using Mentor ModelSim
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---
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* Note:
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- Please **ONLY** place folders under this directory.
README should be the **ONLY** file under this directory
- Each EDA tool should have **independent** workspace in separated directories