2020-10-09 15:16:36 -05:00
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# skywater-openfpga
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FPGA tape-outs using the open-source Skywater 130nm PDK and OpenFPGA
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2020-10-09 23:17:00 -05:00
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* Keep this folder clean and organized as follows
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- DOC: documentation of the project
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- ARCH: Architecture XML and other input files which OpenFPGA requires to generate Verilog netlists
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- BENCHMARK: Benchmarks to be tested on the FPGA fabric
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- HDL: Hardware description netlists for the FPGA fabrics
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- SDC: design constraints
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- SCRIPT: Scripts to setup, run OpenFPGA etc.
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- TESTBENCH: Verilog testbenches generated by OpenFPGA
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- PDK: Technology files linked from skywater opensource pdk
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- SNPS\_ICC2: scripts and workspace of Synopsys IC Compiler 2
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Keep a README inside the folder about the ICC2 version and how-to-use.
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- MSIM: scripts and workspace of verification using Mentor ModelSim
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* Note:
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- Please **ONLY** place folders under this directory
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README should be the ONLY file under this directory
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- Each EDA tool should have independent workspace in a separated directory
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