mirror of https://github.com/lnis-uofu/SOFA.git
905 lines
49 KiB
Plaintext
905 lines
49 KiB
Plaintext
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/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga/openfpga -f top_run.openfpga
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Reading script file top_run.openfpga...
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___ _____ ____ ____ _
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/ _ \ _ __ ___ _ __ | ___| _ \ / ___| / \
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| | | | '_ \ / _ \ '_ \| |_ | |_) | | _ / _ \
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| |_| | |_) | __/ | | | _| | __/| |_| |/ ___ \
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\___/| .__/ \___|_| |_|_| |_| \____/_/ \_\
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OpenFPGA: An Open-source FPGA IP Generator
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Versatile Place and Route (VPR)
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FPGA-Verilog
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FPGA-SPICE
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FPGA-SDC
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FPGA-Bitstream
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This is a free software under the MIT License
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Copyright (c) 2018 LNIS - The University of Utah
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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Command line to execute: vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off
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VPR FPGA Placement and Routing.
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Version: 0.0.0+48b2bff0
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Revision: 48b2bff0
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Compiled: 2020-09-27T20:43:27
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Compiler: GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64
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Build Info: release VTR_ASSERT_LEVEL=2
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University of Toronto
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verilogtorouting.org
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vtr-users@googlegroups.com
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This is free open source code under MIT license.
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VPR was run with the following command-line:
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vpr /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml top.blif --clock_modeling route --device 2x2 --route_chan_width 40 --absorb_buffer_luts off
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Architecture file: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/vpr_arch.xml
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Circuit name: top
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# Loading Architecture Description
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Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
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Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
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Warning 3: Model 'frac_lut4' input port 'in' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
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Warning 4: Model 'frac_lut4' output port 'lut4_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
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Warning 5: Model 'frac_lut4' output port 'lut3_out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
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# Loading Architecture Description took 0.01 seconds (max_rss 8.8 MiB, delta_rss +0.4 MiB)
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# Building complex block graph
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Warning 6: [LINE 546] false logically-equivalent pin clb[0].I0[1].
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Warning 7: [LINE 546] false logically-equivalent pin clb[0].I0[2].
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Warning 8: [LINE 546] false logically-equivalent pin clb[0].I0[3].
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Warning 9: [LINE 548] false logically-equivalent pin clb[0].I1[1].
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Warning 10: [LINE 548] false logically-equivalent pin clb[0].I1[2].
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Warning 11: [LINE 548] false logically-equivalent pin clb[0].I1[3].
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Warning 12: [LINE 550] false logically-equivalent pin clb[0].I2[1].
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Warning 13: [LINE 550] false logically-equivalent pin clb[0].I2[2].
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Warning 14: [LINE 550] false logically-equivalent pin clb[0].I2[3].
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Warning 15: [LINE 552] false logically-equivalent pin clb[0].I3[1].
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Warning 16: [LINE 552] false logically-equivalent pin clb[0].I3[2].
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Warning 17: [LINE 552] false logically-equivalent pin clb[0].I3[3].
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Warning 18: [LINE 554] false logically-equivalent pin clb[0].I4[1].
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Warning 19: [LINE 554] false logically-equivalent pin clb[0].I4[2].
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Warning 20: [LINE 554] false logically-equivalent pin clb[0].I4[3].
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Warning 21: [LINE 556] false logically-equivalent pin clb[0].I5[1].
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Warning 22: [LINE 556] false logically-equivalent pin clb[0].I5[2].
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Warning 23: [LINE 556] false logically-equivalent pin clb[0].I5[3].
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Warning 24: [LINE 558] false logically-equivalent pin clb[0].I6[1].
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Warning 25: [LINE 558] false logically-equivalent pin clb[0].I6[2].
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Warning 26: [LINE 558] false logically-equivalent pin clb[0].I6[3].
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Warning 27: [LINE 560] false logically-equivalent pin clb[0].I7[1].
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Warning 28: [LINE 560] false logically-equivalent pin clb[0].I7[2].
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Warning 29: [LINE 560] false logically-equivalent pin clb[0].I7[3].
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# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.8 MiB)
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# Load circuit
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# Load circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.3 MiB)
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# Clean circuit
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Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs
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Inferred 0 additional primitive pins as constant generators due to constant inputs
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Swept input(s) : 0
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Swept output(s) : 0 (0 dangling, 0 constant)
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Swept net(s) : 0
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Swept block(s) : 0
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Constant Pins Marked: 0
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# Clean circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB)
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# Compress circuit
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# Compress circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB)
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# Verify circuit
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# Verify circuit took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB)
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Circuit Statistics:
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Blocks: 4
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.input : 2
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.output: 1
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4-LUT : 1
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Nets : 3
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Avg Fanout: 1.0
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Max Fanout: 1.0
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Min Fanout: 1.0
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Netlist Clocks: 0
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# Build Timing Graph
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Timing Graph Nodes: 6
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Timing Graph Edges: 5
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Timing Graph Levels: 4
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# Build Timing Graph took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB)
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Netlist contains 0 clocks
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# Load Timing Constraints
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SDC file 'top.sdc' not found
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Setting default timing constraints:
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* constrain all primay inputs and primary outputs on a virtual external clock 'virtual_io_clock'
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* optimize virtual clock to run as fast as possible
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Timing constraints created 1 clocks
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Constrained Clock 'virtual_io_clock' (Virtual Clock)
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# Load Timing Constraints took 0.00 seconds (max_rss 9.8 MiB, delta_rss +0.0 MiB)
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Timing analysis: ON
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Circuit netlist file: top.net
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Circuit placement file: top.place
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Circuit routing file: top.route
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Circuit SDC file: top.sdc
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Packer: ENABLED
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Placer: ENABLED
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Router: ENABLED
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Analysis: ENABLED
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NetlistOpts.abosrb_buffer_luts : false
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NetlistOpts.sweep_dangling_primary_ios : true
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NetlistOpts.sweep_dangling_nets : true
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NetlistOpts.sweep_dangling_blocks : true
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NetlistOpts.sweep_constant_primary_outputs: false
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PackerOpts.allow_unrelated_clustering: auto
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PackerOpts.alpha_clustering: 0.750000
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PackerOpts.beta_clustering: 0.900000
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PackerOpts.cluster_seed_type: BLEND2
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PackerOpts.connection_driven: true
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PackerOpts.global_clocks: true
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PackerOpts.hill_climbing_flag: false
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PackerOpts.inter_cluster_net_delay: 1.000000
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PackerOpts.timing_driven: true
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PackerOpts.target_external_pin_util: auto
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PlacerOpts.place_freq: PLACE_ONCE
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PlacerOpts.place_algorithm: PATH_TIMING_DRIVEN_PLACE
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PlacerOpts.pad_loc_type: FREE
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PlacerOpts.place_cost_exp: 1.000000
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PlacerOpts.place_chan_width: 40
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PlacerOpts.inner_loop_recompute_divider: 0
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PlacerOpts.recompute_crit_iter: 1
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PlacerOpts.timing_tradeoff: 0.500000
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PlacerOpts.td_place_exp_first: 1.000000
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PlacerOpts.td_place_exp_last: 8.000000
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PlaceOpts.seed: 1
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AnnealSched.type: AUTO_SCHED
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AnnealSched.inner_num: 1.000000
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RouterOpts.route_type: DETAILED
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RouterOpts.router_algorithm: TIMING_DRIVEN
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RouterOpts.base_cost_type: DELAY_NORMALIZED_LENGTH
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RouterOpts.fixed_channel_width: 40
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RouterOpts.trim_empty_chan: false
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RouterOpts.trim_obs_chan: false
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RouterOpts.acc_fac: 1.000000
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RouterOpts.bb_factor: 3
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RouterOpts.bend_cost: 0.000000
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RouterOpts.first_iter_pres_fac: 0.000000
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RouterOpts.initial_pres_fac: 0.500000
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RouterOpts.pres_fac_mult: 1.300000
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RouterOpts.max_router_iterations: 50
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RouterOpts.min_incremental_reroute_fanout: 16
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RouterOpts.astar_fac: 1.200000
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RouterOpts.criticality_exp: 1.000000
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RouterOpts.max_criticality: 0.990000
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RouterOpts.routing_failure_predictor = SAFE
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RouterOpts.routing_budgets_algorithm = DISABLE
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AnalysisOpts.gen_post_synthesis_netlist: false
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RoutingArch.directionality: UNI_DIRECTIONAL
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RoutingArch.switch_block_type: WILTON
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RoutingArch.Fs: 3
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# Packing
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Begin packing 'top.blif'.
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After removing unused inputs...
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total blocks: 4, total nets: 3, total inputs: 2, total outputs: 1
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Begin prepacking.
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Finish prepacking.
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Using inter-cluster delay: 1.33777e-09
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Packing with pin utilization targets: io:1,1 clb:0.8,1
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Packing with high fanout thresholds: io:128 clb:32
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Not enough resources expand FPGA size to (4 x 4)
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Complex block 0: 'c' (clb) .
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Complex block 1: 'out:c' (io) .
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Complex block 2: 'a' (io) .
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Complex block 3: 'b' (io) .
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Pb types usage...
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inpad : 2
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outpad : 1
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fle : 1
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clb : 1
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lut3inter : 1
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ble3 : 1
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io : 3
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lut3 : 1
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lut : 1
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Logic Element (fle) detailed count:
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Total number of Logic Elements used : 1
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LEs used for logic and registers : 0
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LEs used for logic only : 1
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LEs used for registers only : 0
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EMPTY: # blocks: 0, average # input + clock pins used: 0, average # output pins used: 0
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io: # blocks: 3, average # input + clock pins used: 0.333333, average # output pins used: 0.666667
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clb: # blocks: 1, average # input + clock pins used: 2, average # output pins used: 1
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Absorbed logical nets 0 out of 3 nets, 3 nets not absorbed.
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FPGA sized to 4 x 4 (2x2)
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Device Utilization: 0.25 (target 1.00)
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Block Utilization: 0.38 Type: io
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Block Utilization: 0.25 Type: clb
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Netlist conversion complete.
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# Packing took 0.01 seconds (max_rss 10.5 MiB, delta_rss +0.7 MiB)
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# Load Packing
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Begin loading packed FPGA netlist file.
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Netlist generated from file 'top.net'.
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Detected 0 constant generators (to see names run with higher pack verbosity)
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Finished loading packed FPGA netlist file (took 0.02 seconds).
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Warning 30: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
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# Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB)
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Warning 31: Netlist contains 0 global net to non-global architecture pin connections
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Netlist num_nets: 3
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Netlist num_blocks: 4
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Netlist EMPTY blocks: 0.
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Netlist io blocks: 3.
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Netlist clb blocks: 1.
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Netlist inputs pins: 2
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Netlist output pins: 1
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# Create Device
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## Build Device Grid
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FPGA sized to 4 x 4: 16 grid tiles (2x2)
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Resource usage...
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Netlist
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3 blocks of type: io
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Architecture
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8 blocks of type: io
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Netlist
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1 blocks of type: clb
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Architecture
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4 blocks of type: clb
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Device Utilization: 0.25 (target 1.00)
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Physical Tile io:
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Block Utilization: 0.38 Logical Block: io
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Physical Tile clb:
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Block Utilization: 0.25 Logical Block: clb
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## Build Device Grid took 0.00 seconds (max_rss 10.6 MiB, delta_rss +0.0 MiB)
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## Build tileable routing resource graph
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X-direction routing channel width is 40
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Y-direction routing channel width is 40
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Warning 32: in check_rr_node: RR node: 57 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
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Warning 33: in check_rr_node: RR node: 58 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges.
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Warning 34: in check_rr_node: RR node: 139 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
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Warning 35: in check_rr_node: RR node: 140 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges.
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Warning 36: in check_rr_graph: fringe node 452 CHANX at (1,1) has no fanin.
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This is possible on a fringe node based on low Fc_out, N, and certain lengths.
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## Build tileable routing resource graph took 0.01 seconds (max_rss 11.1 MiB, delta_rss +0.5 MiB)
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RR Graph Nodes: 684
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RR Graph Edges: 2780
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# Create Device took 0.01 seconds (max_rss 11.1 MiB, delta_rss +0.5 MiB)
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# Placement
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## Computing placement delta delay look-up
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### Build routing resource graph
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Warning 37: in check_rr_node: RR node: 109 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
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Warning 38: in check_rr_node: RR node: 110 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges.
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Warning 39: in check_rr_node: RR node: 293 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
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Warning 40: in check_rr_node: RR node: 294 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges.
|
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Warning 41: in check_rr_graph: fringe node 2 IPIN at (0,1) has no fanin.
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This is possible on a fringe node based on low Fc_out, N, and certain lengths.
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### Build routing resource graph took 0.00 seconds (max_rss 11.1 MiB, delta_rss +0.0 MiB)
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RR Graph Nodes: 732
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RR Graph Edges: 2188
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### Computing delta delays
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### Computing delta delays took 0.00 seconds (max_rss 11.4 MiB, delta_rss +0.3 MiB)
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## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.4 MiB, delta_rss +0.3 MiB)
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||
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There are 3 point to point connections in this circuit.
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BB estimate of min-dist (placement) wire length: 11
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Completed placement consistency check successfully.
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Initial placement cost: 1 bb_cost: 0.275 td_cost: 5.6541e-10
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Initial placement estimated Critical Path Delay (CPD): 0.69331 ns
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Initial placement estimated setup Total Negative Slack (sTNS): -0.69331 ns
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Initial placement estimated setup Worst Negative Slack (sWNS): -0.69331 ns
|
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Initial placement estimated setup slack histogram:
|
||
|
[ -6.9e-10: -6.9e-10) 1 (100.0%) |**************************************************
|
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[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
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[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
Placement contains 0 placement macros involving 0 blocks (average macro size -nan)
|
||
|
|
||
|
------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
|
||
|
T Av Cost Av BB Cost Av TD Cost CPD sTNS sWNS Ac Rate Std Dev R lim Crit Exp Tot Moves Alpha
|
||
|
------- ------- ---------- ---------- ------- ---------- -------- ------- ------- ------ -------- --------- ------
|
||
|
5.6e-01 0.892 0.21 5.1708e-10 0.693 -0.693 -0.693 1.000 0.0754 3.0 1.00 6 0.500
|
||
|
2.8e-01 1.001 0.25 5.8474e-10 0.693 -0.693 -0.693 1.000 0.1044 3.0 1.00 12 0.500
|
||
|
1.4e-01 0.828 0.19 5.1901e-10 0.751 -0.751 -0.751 0.833 0.0971 3.0 1.00 18 0.900
|
||
|
1.3e-01 1.119 0.21 5.3388e-10 0.693 -0.693 -0.693 0.500 0.0412 3.0 1.00 24 0.950
|
||
|
1.2e-01 1.017 0.24 5.3998e-10 0.693 -0.693 -0.693 0.833 0.0366 3.0 1.00 30 0.900
|
||
|
1.1e-01 0.960 0.24 5.3641e-10 0.693 -0.693 -0.693 1.000 0.0433 3.0 1.00 36 0.500
|
||
|
5.4e-02 0.970 0.21 4.9164e-10 0.693 -0.693 -0.693 0.667 0.0405 3.0 1.00 42 0.950
|
||
|
5.1e-02 0.974 0.19 4.4803e-10 0.635 -0.635 -0.635 0.667 0.0470 3.0 1.00 48 0.950
|
||
|
4.9e-02 0.999 0.18 4.3485e-10 0.635 -0.635 -0.635 0.333 0.0019 3.0 1.00 54 0.950
|
||
|
4.6e-02 1.063 0.19 4.5701e-10 0.635 -0.635 -0.635 0.500 0.0549 2.7 2.12 60 0.950
|
||
|
4.4e-02 1.019 0.21 4.9794e-10 0.693 -0.693 -0.693 0.667 0.0458 2.8 1.56 66 0.950
|
||
|
4.2e-02 1.043 0.21 5.1943e-10 0.693 -0.693 -0.693 0.667 0.0215 3.0 1.00 72 0.950
|
||
|
4.0e-02 0.903 0.18 4.7533e-10 0.751 -0.751 -0.751 0.500 0.0052 3.0 1.00 78 0.950
|
||
|
3.8e-02 1.042 0.20 4.4941e-10 0.693 -0.693 -0.693 0.333 0.0000 3.0 1.00 84 0.950
|
||
|
3.6e-02 1.000 0.20 4.2544e-10 0.635 -0.635 -0.635 0.167 0.0000 2.7 2.12 90 0.950
|
||
|
3.4e-02 1.069 0.22 4.4576e-10 0.635 -0.635 -0.635 0.667 0.0458 1.9 4.68 96 0.950
|
||
|
3.2e-02 0.969 0.21 4.6916e-10 0.693 -0.693 -0.693 0.667 0.0361 2.4 3.14 102 0.950
|
||
|
3.1e-02 0.968 0.19 4.7066e-10 0.693 -0.693 -0.693 0.500 0.0537 2.9 1.24 108 0.950
|
||
|
2.9e-02 0.997 0.18 4.322e-10 0.635 -0.635 -0.635 0.500 0.0000 3.0 1.00 114 0.950
|
||
|
2.8e-02 0.999 0.18 4.3485e-10 0.635 -0.635 -0.635 0.333 0.0019 3.0 1.00 120 0.950
|
||
|
2.6e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 2.7 2.12 126 0.950
|
||
|
2.5e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 2.8 1.56 132 0.950
|
||
|
2.4e-02 0.994 0.18 4.0763e-10 0.635 -0.635 -0.635 0.167 0.0000 2.5 2.62 138 0.950
|
||
|
2.3e-02 0.996 0.18 3.9202e-10 0.635 -0.635 -0.635 0.500 0.0064 1.8 5.05 144 0.950
|
||
|
2.1e-02 1.000 0.18 4.0247e-10 0.635 -0.635 -0.635 0.333 0.0000 2.0 4.66 150 0.950
|
||
|
2.0e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.7 5.39 156 0.950
|
||
|
1.9e-02 1.071 0.20 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.3 7.06 162 0.950
|
||
|
1.8e-02 0.967 0.18 5.0741e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 6.79 168 0.950
|
||
|
1.7e-02 0.985 0.18 4.7841e-10 0.693 -0.693 -0.693 0.333 0.0205 1.0 8.00 174 0.950
|
||
|
1.7e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.0 8.00 180 0.950
|
||
|
1.6e-02 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 186 0.950
|
||
|
1.5e-02 0.989 0.18 3.5797e-10 0.635 -0.635 -0.635 0.667 0.0076 1.1 7.79 192 0.950
|
||
|
1.4e-02 1.000 0.18 3.8602e-10 0.635 -0.635 -0.635 0.667 0.0000 1.3 6.95 198 0.950
|
||
|
1.3e-02 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.6 5.92 204 0.950
|
||
|
1.3e-02 0.991 0.18 3.7094e-10 0.635 -0.635 -0.635 0.500 0.0078 1.4 6.51 210 0.950
|
||
|
1.2e-02 0.995 0.18 3.809e-10 0.635 -0.635 -0.635 0.333 0.0113 1.5 6.21 216 0.950
|
||
|
1.2e-02 1.000 0.18 4.1466e-10 0.693 -0.693 -0.693 0.167 0.0000 1.3 6.78 222 0.950
|
||
|
1.1e-02 0.971 0.18 3.491e-10 0.693 -0.693 -0.693 0.500 0.0000 1.0 8.00 228 0.950
|
||
|
1.0e-02 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.79 234 0.950
|
||
|
9.9e-03 1.015 0.18 4.086e-10 0.635 -0.635 -0.635 0.333 0.0205 1.0 8.00 240 0.950
|
||
|
9.4e-03 0.985 0.18 4.7841e-10 0.693 -0.693 -0.693 0.333 0.0205 1.0 8.00 246 0.950
|
||
|
9.0e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.667 0.0000 1.0 8.00 252 0.950
|
||
|
8.5e-03 1.000 0.18 3.8439e-10 0.635 -0.635 -0.635 0.333 0.0000 1.2 7.21 258 0.950
|
||
|
8.1e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.66 264 0.950
|
||
|
7.7e-03 1.000 0.18 3.8297e-10 0.635 -0.635 -0.635 0.167 0.0000 1.2 7.43 270 0.950
|
||
|
7.3e-03 0.992 0.18 3.6408e-10 0.635 -0.635 -0.635 0.667 0.0090 1.0 8.00 276 0.950
|
||
|
6.9e-03 1.000 0.18 3.8439e-10 0.635 -0.635 -0.635 0.500 0.0000 1.2 7.21 282 0.950
|
||
|
6.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.3 6.95 288 0.950
|
||
|
6.3e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.4 6.68 294 0.950
|
||
|
5.9e-03 1.000 0.18 3.8973e-10 0.635 -0.635 -0.635 0.500 0.0000 1.5 6.39 300 0.950
|
||
|
5.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.5 6.08 306 0.950
|
||
|
5.4e-03 0.995 0.18 3.788e-10 0.635 -0.635 -0.635 0.500 0.0079 1.4 6.66 312 0.950
|
||
|
5.1e-03 1.000 0.18 3.8986e-10 0.635 -0.635 -0.635 0.167 0.0000 1.5 6.37 318 0.950
|
||
|
4.8e-03 1.000 0.18 3.8095e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.77 324 0.950
|
||
|
4.6e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.55 330 0.950
|
||
|
4.4e-03 0.995 0.18 3.7402e-10 0.635 -0.635 -0.635 0.500 0.0084 1.2 7.31 336 0.950
|
||
|
4.1e-03 0.986 0.18 3.5684e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 7.06 342 0.950
|
||
|
3.9e-03 0.984 0.18 3.4857e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 348 0.950
|
||
|
3.7e-03 0.985 0.18 3.5034e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.79 354 0.950
|
||
|
3.6e-03 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 360 0.950
|
||
|
3.4e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 366 0.950
|
||
|
3.2e-03 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.79 372 0.950
|
||
|
3.0e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.1 7.57 378 0.950
|
||
|
2.9e-03 0.995 0.18 3.7386e-10 0.635 -0.635 -0.635 0.500 0.0084 1.2 7.33 384 0.950
|
||
|
2.8e-03 0.990 0.18 3.6614e-10 0.635 -0.635 -0.635 0.500 0.0082 1.3 7.08 390 0.950
|
||
|
2.6e-03 1.000 0.18 3.8688e-10 0.635 -0.635 -0.635 0.167 0.0000 1.3 6.82 396 0.950
|
||
|
2.5e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 402 0.950
|
||
|
2.4e-03 1.000 0.18 3.8083e-10 0.635 -0.635 -0.635 0.000 0.0000 1.1 7.79 408 0.950
|
||
|
2.2e-03 0.984 0.18 3.4857e-10 0.635 -0.635 -0.635 0.500 0.0000 1.0 8.00 414 0.950
|
||
|
2.1e-03 0.995 0.18 3.7067e-10 0.635 -0.635 -0.635 0.500 0.0088 1.1 7.79 420 0.950
|
||
|
2.0e-03 0.985 0.18 3.5227e-10 0.635 -0.635 -0.635 0.333 0.0000 1.1 7.57 426 0.950
|
||
|
1.9e-03 0.992 0.18 3.6418e-10 0.635 -0.635 -0.635 0.333 0.0110 1.0 7.99 432 0.950
|
||
|
1.8e-03 1.000 0.18 3.796e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 438 0.950
|
||
|
1.7e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.333 0.0000 1.0 8.00 444 0.950
|
||
|
1.7e-03 1.000 0.18 4.4941e-10 0.635 -0.635 -0.635 0.167 0.0000 1.0 8.00 450 0.000
|
||
|
|
||
|
BB estimate of min-dist (placement) wire length: 7
|
||
|
|
||
|
Completed placement consistency check successfully.
|
||
|
|
||
|
Swaps called: 454
|
||
|
|
||
|
Placement estimated critical path delay: 0.63531 ns
|
||
|
Placement estimated setup Total Negative Slack (sTNS): -0.63531 ns
|
||
|
Placement estimated setup Worst Negative Slack (sWNS): -0.63531 ns
|
||
|
|
||
|
Placement estimated setup slack histogram:
|
||
|
[ -6.4e-10: -6.4e-10) 1 (100.0%) |**************************************************
|
||
|
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) |
|
||
|
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) |
|
||
|
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) |
|
||
|
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) |
|
||
|
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) |
|
||
|
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) |
|
||
|
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) |
|
||
|
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) |
|
||
|
[ -6.4e-10: -6.4e-10) 0 ( 0.0%) |
|
||
|
|
||
|
Placement cost: 1, bb_cost: 0.175, td_cost: 4.4941e-10,
|
||
|
|
||
|
Placement resource usage:
|
||
|
io implemented as io : 3
|
||
|
clb implemented as clb: 1
|
||
|
|
||
|
Placement number of temperatures: 75
|
||
|
Placement total # of swap attempts: 454
|
||
|
Swaps accepted: 208 (45.8 %)
|
||
|
Swaps rejected: 246 (54.2 %)
|
||
|
Swaps aborted : 0 ( 0.0 %)
|
||
|
|
||
|
Aborted Move Reasons:
|
||
|
# Placement took 0.01 seconds (max_rss 11.6 MiB, delta_rss +0.5 MiB)
|
||
|
|
||
|
# Routing
|
||
|
## Build tileable routing resource graph
|
||
|
X-direction routing channel width is 40
|
||
|
Y-direction routing channel width is 40
|
||
|
Warning 42: in check_rr_node: RR node: 57 type: OPIN location: (1,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
|
||
|
Warning 43: in check_rr_node: RR node: 58 type: OPIN location: (1,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges.
|
||
|
Warning 44: in check_rr_node: RR node: 139 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges.
|
||
|
Warning 45: in check_rr_node: RR node: 140 type: OPIN location: (2,1) pin: 51 pin_name: clb.scout[0] capacity: 1 has no out-going edges.
|
||
|
Warning 46: in check_rr_graph: fringe node 452 CHANX at (1,1) has no fanin.
|
||
|
This is possible on a fringe node based on low Fc_out, N, and certain lengths.
|
||
|
## Build tileable routing resource graph took 0.01 seconds (max_rss 11.6 MiB, delta_rss +0.0 MiB)
|
||
|
RR Graph Nodes: 684
|
||
|
RR Graph Edges: 2780
|
||
|
Confirming router algorithm: TIMING_DRIVEN.
|
||
|
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
|
||
|
Iter Time pres BBs Heap Re-Rtd Re-Rtd Overused RR Nodes Wirelength CPD sTNS sWNS hTNS hWNS Est Succ
|
||
|
(sec) fac Updt push Nets Conns (ns) (ns) (ns) (ns) (ns) Iter
|
||
|
---- ------ ------- ---- ------- ------- ------- ----------------- --------------- -------- ---------- ---------- ---------- ---------- --------
|
||
|
1 0.0 0.0 0 80 3 3 0 ( 0.000%) 6 ( 1.2%) 0.693 -0.6933 -0.693 0.000 0.000 N/A
|
||
|
Restoring best routing
|
||
|
Critical path: 0.69331 ns
|
||
|
Successfully routed after 1 routing iterations.
|
||
|
Router Stats: total_nets_routed: 3 total_connections_routed: 3 total_heap_pushes: 80 total_heap_pops: 45
|
||
|
# Routing took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.1 MiB)
|
||
|
|
||
|
Checking to ensure routing is legal...
|
||
|
Completed routing consistency check successfully.
|
||
|
|
||
|
Serial number (magic cookie) for the routing is: -11536
|
||
|
Circuit successfully routed with a channel width factor of 40.
|
||
|
|
||
|
Average number of bends per net: 0.333333 Maximum # of bends: 1
|
||
|
|
||
|
Number of global nets: 0
|
||
|
Number of routed nets (nonglobal): 3
|
||
|
Wire length results (in units of 1 clb segments)...
|
||
|
Total wirelength: 6, average net length: 2.00000
|
||
|
Maximum net length: 3
|
||
|
|
||
|
Wire length results in terms of physical segments...
|
||
|
Total wiring segments used: 5, average wire segments per net: 1.66667
|
||
|
Maximum segments used by a net: 2
|
||
|
Total local nets with reserved CLB opins: 0
|
||
|
|
||
|
Routing channel utilization histogram:
|
||
|
[ 1: inf) 0 ( 0.0%) |
|
||
|
[ 0.9: 1) 0 ( 0.0%) |
|
||
|
[ 0.8: 0.9) 0 ( 0.0%) |
|
||
|
[ 0.7: 0.8) 0 ( 0.0%) |
|
||
|
[ 0.5: 0.6) 0 ( 0.0%) |
|
||
|
[ 0.4: 0.5) 0 ( 0.0%) |
|
||
|
[ 0.3: 0.4) 0 ( 0.0%) |
|
||
|
[ 0.2: 0.3) 0 ( 0.0%) |
|
||
|
[ 0.1: 0.2) 0 ( 0.0%) |
|
||
|
[ 0: 0.1) 18 (100.0%) |************************************************
|
||
|
Maximum routing channel utilization: 0.075 at (1,0)
|
||
|
|
||
|
X - Directed channels: j max occ ave occ capacity
|
||
|
---- ------- ------- --------
|
||
|
0 3 1.250 40
|
||
|
1 0 0.000 40
|
||
|
2 0 0.000 40
|
||
|
Y - Directed channels: i max occ ave occ capacity
|
||
|
---- ------- ------- --------
|
||
|
0 1 0.250 40
|
||
|
1 0 0.000 40
|
||
|
2 0 0.000 40
|
||
|
|
||
|
Total tracks in x-direction: 120, in y-direction: 120
|
||
|
|
||
|
Logic area (in minimum width transistor areas, excludes I/Os and empty grid tiles)...
|
||
|
Total logic block area (Warning, need to add pitch of routing to blocks with height > 3): 215576
|
||
|
Total used logic block area: 53894
|
||
|
|
||
|
Routing area (in minimum width transistor areas)...
|
||
|
Total routing area: 22261.4, per logic tile: 1391.34
|
||
|
|
||
|
Segment usage by type (index): type utilization
|
||
|
---- -----------
|
||
|
0 0.0833
|
||
|
1 0.0278
|
||
|
2 0
|
||
|
|
||
|
Segment usage by length: length utilization
|
||
|
------ -----------
|
||
|
1 0.0833
|
||
|
2 0.0278
|
||
|
4 0
|
||
|
|
||
|
|
||
|
Hold Worst Negative Slack (hWNS): 0 ns
|
||
|
Hold Total Negative Slack (hTNS): 0 ns
|
||
|
|
||
|
Hold slack histogram:
|
||
|
[ 5.5e-10: 5.5e-10) 1 (100.0%) |**************************************************
|
||
|
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) |
|
||
|
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) |
|
||
|
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) |
|
||
|
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) |
|
||
|
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) |
|
||
|
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) |
|
||
|
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) |
|
||
|
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) |
|
||
|
[ 5.5e-10: 5.5e-10) 0 ( 0.0%) |
|
||
|
|
||
|
Final critical path: 0.69331 ns, Fmax: 1442.36 MHz
|
||
|
Setup Worst Negative Slack (sWNS): -0.69331 ns
|
||
|
Setup Total Negative Slack (sTNS): -0.69331 ns
|
||
|
|
||
|
Setup slack histogram:
|
||
|
[ -6.9e-10: -6.9e-10) 1 (100.0%) |**************************************************
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
|
||
|
|
||
|
Timing analysis took 0.000535006 seconds (0.000479183 STA, 5.5823e-05 slack) (80 full updates: 78 setup, 0 hold, 2 combined).
|
||
|
VPR suceeded
|
||
|
The entire flow of VPR took 0.09 seconds (max_rss 11.9 MiB)
|
||
|
|
||
|
Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
|
||
|
|
||
|
Confirm selected options when call command 'read_openfpga_arch':
|
||
|
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
|
||
|
Reading XML architecture '/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml'...
|
||
|
Read OpenFPGA architecture
|
||
|
Warning 47: Automatically set circuit model 'frac_lut4' to be default in its type.
|
||
|
Warning 48: Automatically set circuit model 'sky130_fd_sc_hd__sdfxbp_1' to be default in its type.
|
||
|
Warning 49: Automatically set circuit model 'sky130_fd_sc_hd__dfxbp_1' to be default in its type.
|
||
|
Warning 50: Automatically set circuit model 'GPIO' to be default in its type.
|
||
|
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree' port 'sram')
|
||
|
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree_tapbuf' port 'sram')
|
||
|
Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'frac_lut4' port 'sram')
|
||
|
Read OpenFPGA architecture took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.3 MiB)
|
||
|
Check circuit library
|
||
|
Checking circuit library passed.
|
||
|
Check circuit library took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB)
|
||
|
Found 0 errors when checking configurable memory circuit models!
|
||
|
|
||
|
Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||
|
|
||
|
Confirm selected options when call command 'read_openfpga_simulation_setting':
|
||
|
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||
|
Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'...
|
||
|
Read OpenFPGA simulation settings
|
||
|
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB)
|
||
|
|
||
|
Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges
|
||
|
|
||
|
Confirm selected options when call command 'link_openfpga_arch':
|
||
|
--activity_file: top_ace_out.act
|
||
|
--sort_gsb_chan_node_in_edges: on
|
||
|
--verbose: off
|
||
|
Link OpenFPGA architecture to VPR architecture
|
||
|
|
||
|
Building annotation for physical modes in pb_type...Done
|
||
|
Check physical mode annotation for pb_types passed.
|
||
|
|
||
|
Building annotation about physical types for pb_type interconnection...Done
|
||
|
|
||
|
Building annotation between operating and physical pb_types...Done
|
||
|
Check physical pb_type annotation for pb_types passed.
|
||
|
|
||
|
Building annotation between physical pb_types and circuit models...Done
|
||
|
Check physical pb_type annotation for circuit model passed.
|
||
|
|
||
|
Building annotation between physical pb_types and mode selection bits...Done
|
||
|
Check pb_type annotation for mode selection bits passed.
|
||
|
Assigning unique indices for primitive pb_graph nodes...Done
|
||
|
Binding operating pb_graph nodes/pins to physical pb_graph nodes/pins...Done
|
||
|
Check pb_graph annotation for physical nodes and pins passed.
|
||
|
Binded 4 routing resource graph switches to circuit models
|
||
|
Binded 3 routing segments to circuit models
|
||
|
Binded 2 direct connections to circuit models
|
||
|
Annotating rr_node with routed nets...Done with 11 nodes mapping
|
||
|
Annotating previous nodes for rr_node...Warning 51: Override the previous node '89' by previous node '90' for node '37' with in routing context annotation!
|
||
|
Done with 14 nodes mapping
|
||
|
# Build General Switch Block(GSB) annotation on top of routing resource graph
|
||
|
[11%] Backannotated GSB[0][0]
|
||
|
[22%] Backannotated GSB[0][1]
|
||
|
[33%] Backannotated GSB[0][2]
|
||
|
[44%] Backannotated GSB[1][0]
|
||
|
[55%] Backannotated GSB[1][1]
|
||
|
[66%] Backannotated GSB[1][2]
|
||
|
[77%] Backannotated GSB[2][0]
|
||
|
[88%] Backannotated GSB[2][1]
|
||
|
[100%] Backannotated GSB[2][2]
|
||
|
Backannotated 9 General Switch Blocks (GSBs).
|
||
|
# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB)
|
||
|
# Sort incoming edges for each routing track output node of General Switch Block(GSB)
|
||
|
[11%] Sorted edges for GSB[0][0]
|
||
|
[22%] Sorted edges for GSB[0][1]
|
||
|
[33%] Sorted edges for GSB[0][2]
|
||
|
[44%] Sorted edges for GSB[1][0]
|
||
|
[55%] Sorted edges for GSB[1][1]
|
||
|
[66%] Sorted edges for GSB[1][2]
|
||
|
[77%] Sorted edges for GSB[2][0]
|
||
|
[88%] Sorted edges for GSB[2][1]
|
||
|
[100%] Sorted edges for GSB[2][2]
|
||
|
Sorted edges for 9 General Switch Blocks (GSBs).
|
||
|
# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.2 MiB, delta_rss +0.0 MiB)
|
||
|
# Build a library of physical multiplexers
|
||
|
Built a multiplexer library of 14 physical multiplexers.
|
||
|
Maximum multiplexer size is 17.
|
||
|
# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.3 MiB)
|
||
|
# Build the annotation about direct connection between tiles
|
||
|
Built 6 tile-to-tile direct connections
|
||
|
# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.0 MiB)
|
||
|
Building annotation for mapped blocks on grid locations...Done
|
||
|
User specified the operating clock frequency to use VPR results
|
||
|
Use VPR critical path delay 8.31972e-19 [ns] with a 20 [%] slack in OpenFPGA.
|
||
|
Will apply operating clock frequency 1201.96 [MHz] to simulations
|
||
|
User specified the number of operating clock cycles to be inferred from signal activities
|
||
|
Average net density: 0.42
|
||
|
Median net density: 0.00
|
||
|
Average net density after weighting: 0.42
|
||
|
Will apply 2 operating clock cycles to simulations
|
||
|
Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.3 MiB)
|
||
|
|
||
|
Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_task/arch/fabric_key.xml
|
||
|
|
||
|
Confirm selected options when call command 'build_fabric':
|
||
|
--frame_view: off
|
||
|
--compress_routing: on
|
||
|
--duplicate_grid_pin: on
|
||
|
--load_fabric_key: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_task/arch/fabric_key.xml
|
||
|
--write_fabric_key: off
|
||
|
--generate_random_fabric_key: off
|
||
|
--verbose: off
|
||
|
Identify unique General Switch Blocks (GSBs)
|
||
|
Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00%)
|
||
|
Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB)
|
||
|
|
||
|
Read Fabric Key
|
||
|
Read Fabric Key took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB)
|
||
|
|
||
|
Build fabric module graph
|
||
|
# Build constant generator modules
|
||
|
# Build constant generator modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB)
|
||
|
# Build user-defined modules
|
||
|
# Build user-defined modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB)
|
||
|
# Build essential (inverter/buffer/logic gate) modules
|
||
|
# Build essential (inverter/buffer/logic gate) modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB)
|
||
|
# Build local encoder (for multiplexers) modules
|
||
|
# Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB)
|
||
|
# Building multiplexer modules
|
||
|
# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.3 MiB)
|
||
|
# Build Look-Up Table (LUT) modules
|
||
|
# Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.0 MiB)
|
||
|
# Build wire modules
|
||
|
# Build wire modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.0 MiB)
|
||
|
# Build memory modules
|
||
|
# Build memory modules took 0.00 seconds (max_rss 13.1 MiB, delta_rss +0.3 MiB)
|
||
|
# Build grid modules
|
||
|
Building logical tiles...Done
|
||
|
Building physical tiles...Done
|
||
|
# Build grid modules took 0.00 seconds (max_rss 13.6 MiB, delta_rss +0.5 MiB)
|
||
|
# Build unique routing modules...
|
||
|
# Build unique routing modules... took 0.01 seconds (max_rss 15.9 MiB, delta_rss +2.3 MiB)
|
||
|
# Build FPGA fabric module
|
||
|
## Add grid instances to top module
|
||
|
## Add grid instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB)
|
||
|
## Add switch block instances to top module
|
||
|
## Add switch block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB)
|
||
|
## Add connection block instances to top module
|
||
|
## Add connection block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB)
|
||
|
## Add connection block instances to top module
|
||
|
## Add connection block instances to top module took 0.00 seconds (max_rss 15.9 MiB, delta_rss +0.0 MiB)
|
||
|
## Add module nets between grids and GSBs
|
||
|
## Add module nets between grids and GSBs took 0.00 seconds (max_rss 16.7 MiB, delta_rss +0.5 MiB)
|
||
|
## Add module nets for inter-tile connections
|
||
|
## Add module nets for inter-tile connections took 0.00 seconds (max_rss 16.7 MiB, delta_rss +0.0 MiB)
|
||
|
## Add module nets for configuration buses
|
||
|
## Add module nets for configuration buses took 0.00 seconds (max_rss 16.8 MiB, delta_rss +0.1 MiB)
|
||
|
# Build FPGA fabric module took 0.01 seconds (max_rss 16.8 MiB, delta_rss +0.9 MiB)
|
||
|
Build fabric module graph took 0.02 seconds (max_rss 16.8 MiB, delta_rss +4.2 MiB)
|
||
|
|
||
|
Command line to execute: repack
|
||
|
|
||
|
Confirm selected options when call command 'repack':
|
||
|
--verbose: off
|
||
|
Build routing resource graph for the physical implementation of logical tile
|
||
|
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.3 MiB)
|
||
|
Repack clustered blocks to physical implementation of logical tile
|
||
|
Repack clustered block 'c'...Done
|
||
|
Repack clustered block 'out:c'...Done
|
||
|
Repack clustered block 'a'...Done
|
||
|
Repack clustered block 'b'...Done
|
||
|
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.0 MiB)
|
||
|
Build truth tables for physical LUTs
|
||
|
Build truth tables for physical LUTs took 0.00 seconds (max_rss 17.1 MiB, delta_rss +0.0 MiB)
|
||
|
|
||
|
Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml
|
||
|
|
||
|
Confirm selected options when call command 'build_architecture_bitstream':
|
||
|
--write_file: fabric_indepenent_bitstream.xml
|
||
|
--read_file: off
|
||
|
--verbose: off
|
||
|
|
||
|
Build fabric-independent bitstream for implementation 'top'
|
||
|
|
||
|
Generating bitstream for Switch blocks...Done
|
||
|
Generating bitstream for X-direction Connection blocks ...Done
|
||
|
Generating bitstream for Y-direction Connection blocks ...Done
|
||
|
|
||
|
Build fabric-independent bitstream for implementation 'top'
|
||
|
took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.3 MiB)
|
||
|
Warning 52: Directory path is empty and nothing will be created.
|
||
|
Write 2009 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
|
||
|
Write 2009 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.02 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
|
||
|
|
||
|
Command line to execute: build_fabric_bitstream
|
||
|
|
||
|
Confirm selected options when call command 'build_fabric_bitstream':
|
||
|
--verbose: off
|
||
|
|
||
|
Build fabric dependent bitstream
|
||
|
|
||
|
|
||
|
Build fabric dependent bitstream
|
||
|
took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
|
||
|
|
||
|
Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
|
||
|
|
||
|
Confirm selected options when call command 'write_fabric_bitstream':
|
||
|
--file, -f: fabric_bitstream.bit
|
||
|
--format: plain_text
|
||
|
--verbose: off
|
||
|
Warning 53: Directory path is empty and nothing will be created.
|
||
|
Write 2009 fabric bitstream into plain text file 'fabric_bitstream.bit'
|
||
|
Write 2009 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
|
||
|
|
||
|
Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml
|
||
|
|
||
|
Confirm selected options when call command 'write_fabric_bitstream':
|
||
|
--file, -f: fabric_bitstream.xml
|
||
|
--format: xml
|
||
|
--verbose: off
|
||
|
Warning 54: Directory path is empty and nothing will be created.
|
||
|
Write 2009 fabric bitstream into xml file 'fabric_bitstream.xml'
|
||
|
Write 2009 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB)
|
||
|
|
||
|
Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --verbose
|
||
|
|
||
|
Confirm selected options when call command 'write_fabric_verilog':
|
||
|
--file, -f: ./SRC
|
||
|
--explicit_port_mapping: on
|
||
|
--include_timing: on
|
||
|
--include_signal_init: on
|
||
|
--support_icarus_simulator: on
|
||
|
--print_user_defined_template: off
|
||
|
--verbose: on
|
||
|
Write Verilog netlists for FPGA fabric
|
||
|
|
||
|
Succeed to create directory './SRC'
|
||
|
Succeed to create directory './SRC/sub_module'
|
||
|
Succeed to create directory './SRC/lb'
|
||
|
Succeed to create directory './SRC/routing'
|
||
|
Generating Verilog netlist './SRC/sub_module/inv_buf_passgate.v' for essential gates...Done
|
||
|
Writing Verilog netlist for configuration decoders './SRC/sub_module/arch_encoder.v'...Done
|
||
|
Writing Verilog netlist for local decoders for multiplexers './SRC/sub_module/local_encoder.v'...Done
|
||
|
Writing Verilog netlist for Multiplexers './SRC/sub_module/muxes.v' ...Done
|
||
|
Writing Verilog netlist for LUTs './SRC/sub_module/luts.v'...Done
|
||
|
Writing Verilog netlist for wires './SRC/sub_module/wires.v'...Done
|
||
|
Writing Verilog netlist for memories './SRC/sub_module/memories.v' ...Done
|
||
|
|
||
|
Writing logical tiles...
|
||
|
Writing Verilog netlists for logic tile 'io' ...
|
||
|
Writing Verilog netlist './SRC/lb/logical_tile_io_mode_physical__iopad.v' for primitive pb_type 'iopad' ...
|
||
|
Writing Verilog codes of logical tile primitive block 'logical_tile_io_mode_physical__iopad'...Done
|
||
|
Writing Verilog netlist './SRC/lb/logical_tile_io_mode_io_.v' for pb_type 'io' ...
|
||
|
Writing Verilog codes of pb_type 'logical_tile_io_mode_io_'...Done
|
||
|
Done
|
||
|
|
||
|
Writing Verilog netlists for logic tile 'clb' ...
|
||
|
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v' for primitive pb_type 'frac_lut4' ...
|
||
|
Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4'...Done
|
||
|
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v' for pb_type 'frac_logic' ...
|
||
|
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic'...Done
|
||
|
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v' for primitive pb_type 'ff' ...
|
||
|
Writing Verilog codes of logical tile primitive block 'logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff'...Done
|
||
|
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v' for pb_type 'fabric' ...
|
||
|
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle_mode_physical__fabric'...Done
|
||
|
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_default__fle.v' for pb_type 'fle' ...
|
||
|
Writing Verilog codes of pb_type 'logical_tile_clb_mode_default__fle'...Done
|
||
|
Writing Verilog netlist './SRC/lb/logical_tile_clb_mode_clb_.v' for pb_type 'clb' ...
|
||
|
Writing Verilog codes of pb_type 'logical_tile_clb_mode_clb_'...Done
|
||
|
Done
|
||
|
|
||
|
Writing logical tiles...Done
|
||
|
|
||
|
Building physical tiles...
|
||
|
Writing Verilog Netlist './SRC/lb/grid_io_top.v' for physical tile 'io' at top side ...Done
|
||
|
Writing Verilog Netlist './SRC/lb/grid_io_right.v' for physical tile 'io' at right side ...Done
|
||
|
Writing Verilog Netlist './SRC/lb/grid_io_bottom.v' for physical tile 'io' at bottom side ...Done
|
||
|
Writing Verilog Netlist './SRC/lb/grid_io_left.v' for physical tile 'io' at left side ...Done
|
||
|
Writing Verilog Netlist './SRC/lb/grid_clb.v' for physical_tile 'clb'...Done
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Building physical tiles...Done
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Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done
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Written 70 Verilog modules in total
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Write Verilog netlists for FPGA fabric
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took 0.14 seconds (max_rss 17.6 MiB, delta_rss +0.3 MiB)
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Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
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Confirm selected options when call command 'write_verilog_testbench':
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--file, -f: ./SRC
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--reference_benchmark_file_path: top_output_verilog.v
|
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--print_top_testbench: on
|
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--fast_configuration: off
|
||
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--print_formal_verification_top_netlist: off
|
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--print_preconfig_top_testbench: on
|
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--print_simulation_ini: ./SimulationDeck/simulation_deck.ini
|
||
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--explicit_port_mapping: on
|
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--verbose: off
|
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Warning 55: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled
|
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Write Verilog testbenches for FPGA fabric
|
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|
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Warning 56: Directory './SRC' already exists. Will overwrite contents
|
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# Write pre-configured FPGA top-level Verilog netlist for design 'top'
|
||
|
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 0.01 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB)
|
||
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# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top'
|
||
|
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB)
|
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# Write autocheck testbench for FPGA top-level Verilog netlist for 'top'
|
||
|
Will use 2010 configuration clock cycles to top testbench
|
||
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# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.01 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB)
|
||
|
Succeed to create directory './SimulationDeck'
|
||
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# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini'
|
||
|
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB)
|
||
|
Write Verilog testbenches for FPGA fabric
|
||
|
took 0.03 seconds (max_rss 17.6 MiB, delta_rss +0.0 MiB)
|
||
|
|
||
|
Command line to execute: exit
|
||
|
|
||
|
Confirm selected options when call command 'exit':
|
||
|
|
||
|
Finish execution with 0 errors
|
||
|
|
||
|
The entire OpenFPGA flow took 0.22 seconds
|
||
|
|
||
|
Thank you for using OpenFPGA!
|