40 lines
1.5 KiB
Markdown
40 lines
1.5 KiB
Markdown
> ### Motivate of the pull request
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> - [ ] To address an existing issue. If so, please provide a link to the issue: <issue id>
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> - [ ] Breaking new feature. If so, please describe details in the description part.
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> ### Describe the technical details
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> #### What is currently done? (Provide issue link if applicable)
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> <!-- Please provide a list of limitations if not specified in any issue -->
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> <!-- Below is a template, uncomment upon your needs -->
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> <!-- Currently, OpenFPGA has the following limitations: -->
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> <!-- - [ ] technical details about limitation -->
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> <!-- - [ ] more limitations -->
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>
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> #### What does this pull request change?
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> <!-- Please provide a list of highlights of your changes. -->
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> <!-- Below is a template, uncomment upon your needs -->
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> <!-- This PR improves in the following aspects: -->
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> <!-- - [ ] details about the technical highlight -->
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> <!-- - [ ] <more technical highlights -->
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> ### Which part of the code base require a change
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> <!-- In general, modification on existing submodules are not acceptable. You should push changes to upstream. -->
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> - [ ] VPR
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> - [ ] Tileable routing architecture generator
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> - [ ] OpenFPGA libraries
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> - [ ] FPGA-Verilog
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> - [ ] FPGA-Bitstream
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> - [ ] FPGA-SDC
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> - [ ] FPGA-SPICE
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> - [ ] Flow scripts
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> - [ ] Architecture library
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> - [ ] Cell library
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> - [ ] Documentation
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> - [ ] Regression tests
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> - [ ] Continous Integration (CI) scripts
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> ### Impact of the pull request
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> - [ ] Require a change on Quality of Results (QoR)
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> - [ ] Break back-compatibility. If so, please list who may be influenced.
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