OpenFPGA/vpr7_x2p/vpr
tangxifan d2ddbc19a3 refactoring the reserved sram port generation 2019-09-22 16:38:16 -06:00
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ARCH Explicit verilog final push 2019-07-16 13:13:30 -06:00
Circuits Add missing Verilog source, Archictecture folder and Testbenches correction 2019-05-13 16:41:35 -06:00
SRC refactoring the reserved sram port generation 2019-09-22 16:38:16 -06:00
SpiceNetlists Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
VerilogNetlists Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
CMakeLists.txt fix CMakeList bug in disabling VPR graphics 2019-06-15 13:21:25 -06:00
go_fpga_spice.sh Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh rename rr_switch_block to rr_gsb, a generic block 2019-06-06 17:41:01 -06:00
regression_verilog.sh Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00