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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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fe47b3d21f
OpenFPGA
/
vpr7_x2p
/
vpr
History
Baudouin Chauviere
fe47b3d21f
Changing arch from memory dec to scff. Get the bitstream from go.sh
2018-12-06 14:03:17 -07:00
..
Circuits
rename customized vpr7 to vpr7 XML to Production
2018-09-17 23:10:45 -06:00
SRC
Edit auto-generated modelsim script
2018-12-05 16:15:29 -07:00
SpiceNetlists
rename customized vpr7 to vpr7 XML to Production
2018-09-17 23:10:45 -06:00
VerilogNetlists
Add timing and initialization for simulation
2018-12-04 17:32:09 -07:00
Makefile
rename customized vpr7 to vpr7 XML to Production
2018-09-17 23:10:45 -06:00
arch.xml
Changing arch from memory dec to scff. Get the bitstream from go.sh
2018-12-06 14:03:17 -07:00
go.sh
Changing arch from memory dec to scff. Get the bitstream from go.sh
2018-12-06 14:03:17 -07:00
picorv_ace.act
Update on the examples to respect the new syntax
2018-11-19 15:50:29 -07:00
picorv_ace.blif
Update on the examples to respect the new syntax
2018-11-19 15:50:29 -07:00