OpenFPGA/vpr7_rram/vpr/SRC/syn_verilog/verilog_lut.h

8 lines
357 B
C

void dump_verilog_pb_primitive_lut(FILE* fp,
char* subckt_prefix,
t_logical_block* mapped_logical_block,
t_pb_graph_node* cur_pb_graph_node,
int index,
t_spice_model* spice_model);