98 lines
4.1 KiB
C++
98 lines
4.1 KiB
C++
#ifndef OPENFPGA_PORT_H
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#define OPENFPGA_PORT_H
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/********************************************************************
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* Include header files that are required by data structure declaration
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*******************************************************************/
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#include <string>
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#include <vector>
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/* namespace openfpga begins */
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namespace openfpga {
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/* A basic port */
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class BasicPort {
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public: /* Constructors */
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BasicPort();
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BasicPort(const char* name, const size_t& lsb, const size_t& msb);
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BasicPort(const char* name, const size_t& width);
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BasicPort(const std::string& name, const size_t& lsb, const size_t& msb);
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BasicPort(const std::string& name, const size_t& width);
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BasicPort(const BasicPort& basic_port); /* Copy constructor */
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public: /* Overloaded operators */
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bool operator== (const BasicPort& portA) const;
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bool operator< (const BasicPort& portA) const;
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public: /* Accessors */
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size_t get_width() const; /* get the port width */
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size_t get_msb() const; /* get the LSB */
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size_t get_lsb() const; /* get the LSB */
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std::string get_name() const; /* get the name */
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bool is_valid() const; /* check if port size is valid > 0 */
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std::vector<size_t> pins() const; /* Make a range of the pin indices */
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bool mergeable(const BasicPort& portA) const; /* Check if a port can be merged with this port */
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bool contained(const BasicPort& portA) const; /* Check if a port is contained by this port */
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size_t get_origin_port_width() const;
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public: /* Mutators */
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void set(const BasicPort& basic_port); /* copy */
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void set_name(const std::string& name); /* set the port LSB and MSB */
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void set_width(const size_t& width); /* set the port LSB and MSB */
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void set_width(const size_t& lsb, const size_t& msb); /* set the port LSB and MSB */
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void set_lsb(const size_t& lsb);
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void set_msb(const size_t& msb);
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void expand(const size_t& width); /* Increase the port width */
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void revert(); /* Swap lsb and msb */
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bool rotate(const size_t& offset); /* rotate */
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bool counter_rotate(const size_t& offset); /* counter rotate */
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void reset(); /* Reset to initial port */
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void combine(const BasicPort& port); /* Combine two ports */
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void merge(const BasicPort& portA);
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void set_origin_port_width(const size_t& origin_port_width);
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private: /* internal functions */
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void make_invalid(); /* Make a port invalid */
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private: /* Internal Data */
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std::string name_; /* Name of this port */
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size_t msb_; /* Most Significant Bit of this port */
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size_t lsb_; /* Least Significant Bit of this port */
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size_t origin_port_width_; /* Original port width of a port, used by traceback port conversion history */
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};
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/* Configuration ports:
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* 1. reserved configuration port, which is used by RRAM FPGA architecture
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* 2. regular configuration port, which is used by any FPGA architecture
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*/
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class ConfPorts {
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public: /* Constructors */
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ConfPorts(); /* default port */
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ConfPorts(const ConfPorts& conf_ports); /* copy */
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public: /* Accessors */
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size_t get_reserved_port_width() const;
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size_t get_reserved_port_lsb() const;
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size_t get_reserved_port_msb() const;
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size_t get_regular_port_width() const;
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size_t get_regular_port_lsb() const;
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size_t get_regular_port_msb() const;
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public: /* Mutators */
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void set(const ConfPorts& conf_ports);
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void set_reserved_port(size_t width);
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void set_regular_port(size_t width);
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void set_regular_port(size_t lsb, size_t msb);
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void set_regular_port_lsb(size_t lsb);
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void set_regular_port_msb(size_t msb);
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void expand_reserved_port(size_t width); /* Increase the port width of reserved port */
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void expand_regular_port(size_t width); /* Increase the port width of regular port */
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void expand(size_t width); /* Increase the port width of both ports */
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bool rotate_regular_port(size_t offset); /* rotate */
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bool counter_rotate_regular_port(size_t offset); /* counter rotate */
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void reset(); /* Reset to initial port */
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private: /* Internal Data */
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BasicPort reserved_;
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BasicPort regular_;
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};
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/* TODO: create a class for BL and WL ports */
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} /* namespace openfpga ends */
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#endif
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