tangxifan f9fcc6b471 tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation		2020-04-22 18:24:09 -06:00
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OpenFPGAShellScripts	tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation	2020-04-22 18:24:09 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	add register chain and scan chain to Travis CI	2020-04-12 15:28:22 -06:00
arch	add arch file with spy pads	2020-04-22 12:56:09 -06:00
benchmarks	update microbenchmark and2 module name	2020-04-20 13:37:39 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Updated openfpga_flow and task file to support sheel run	2020-04-06 00:34:36 -06:00
openfpga_arch	add arch file with spy pads	2020-04-22 12:56:09 -06:00
scripts	BugFix: The filename in the previous commit	2020-04-15 12:44:22 -06:00
tasks	tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation	2020-04-22 18:24:09 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00