tangxifan f9a2bb0490 Reorganize task directory		2020-07-04 19:06:41 -06:00
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OpenFPGAShellScripts	add bitstream generation only test case to CI	2020-07-02 16:31:22 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	update arch to support reset signal for SRAm	2020-06-11 19:31:14 -06:00
arch/vpr_only_templates	remove obselete codes and update regression tests	2020-07-04 17:31:34 -06:00
benchmarks	start using counter benchmark in regression tests	2020-06-11 19:31:15 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	update sample key	2020-06-27 15:01:12 -06:00
misc	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
openfpga_arch	add readme for OpenFPGA architecture naming	2020-07-01 10:27:21 -06:00
openfpga_simulation_settings	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00
scripts	remove obselete codes and update regression tests	2020-07-04 17:31:34 -06:00
tasks	Reorganize task directory	2020-07-04 19:06:41 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00