103 lines
4.6 KiB
C++
103 lines
4.6 KiB
C++
/*********************************************************************
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* This file includes top-level function to generate Verilog primitive modules
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* and print them to files
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********************************************************************/
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/* Standard header files */
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/* External library header files */
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#include "util.h"
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/* FPGA-Verilog header files */
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#include "verilog_submodule_utils.h"
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#include "verilog_essential_gates.h"
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#include "verilog_decoders.h"
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#include "verilog_mux.h"
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#include "verilog_lut.h"
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#include "verilog_wire.h"
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#include "verilog_memory.h"
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#include "verilog_writer_utils.h"
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/* Header file for this source file */
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#include "verilog_submodules.h"
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/*********************************************************************
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* Top-level function to generate primitive modules:
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* 1. Logic gates: AND/OR, inverter, buffer and transmission-gate/pass-transistor
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* 2. Routing multiplexers
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* 3. Local encoders for routing multiplexers
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* 4. Wires
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* 5. Configuration memory blocks
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* 6. Verilog template
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********************************************************************/
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void print_verilog_submodules(ModuleManager& module_manager,
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const MuxLibrary& mux_lib,
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t_sram_orgz_info* cur_sram_orgz_info,
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const char* verilog_dir,
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const char* submodule_dir,
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const t_arch& Arch,
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const t_syn_verilog_opts& fpga_verilog_opts) {
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/* Register all the user-defined modules in the module manager
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* This should be done prior to other steps in this function,
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* because they will be instanciated by other primitive modules
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*/
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vpr_printf(TIO_MESSAGE_INFO,
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"Registering user-defined modules...\n");
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/* Create a vector to contain all the Verilog netlist names that have been generated in this function */
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std::vector<std::string> netlist_names;
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add_user_defined_verilog_modules(module_manager, Arch.spice->circuit_lib);
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print_verilog_submodule_essentials(module_manager,
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netlist_names,
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std::string(verilog_dir),
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std::string(submodule_dir),
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Arch.spice->circuit_lib);
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/* Routing multiplexers */
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vpr_printf(TIO_MESSAGE_INFO,
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"Generating modules for routing multiplexers...\n");
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/* NOTE: local decoders generation must go before the MUX generation!!!
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* because local decoders modules will be instanciated in the MUX modules
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*/
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print_verilog_submodule_mux_local_decoders(module_manager, netlist_names,
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mux_lib, Arch.spice->circuit_lib,
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std::string(verilog_dir), std::string(submodule_dir));
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print_verilog_submodule_muxes(module_manager, netlist_names, mux_lib, Arch.spice->circuit_lib, cur_sram_orgz_info,
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std::string(verilog_dir), std::string(submodule_dir),
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fpga_verilog_opts.dump_explicit_verilog);
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/* LUTes */
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vpr_printf(TIO_MESSAGE_INFO,
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"Generating modules for LUTs...\n");
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print_verilog_submodule_luts(module_manager, netlist_names, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir),
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fpga_verilog_opts.dump_explicit_verilog);
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/* Hard wires */
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print_verilog_submodule_wires(module_manager, netlist_names, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir));
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/* 4. Memories */
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vpr_printf(TIO_MESSAGE_INFO,
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"Generating modules for configuration memory blocks...\n");
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print_verilog_submodule_memories(module_manager, netlist_names,
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mux_lib, Arch.spice->circuit_lib,
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std::string(verilog_dir), std::string(submodule_dir),
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fpga_verilog_opts.dump_explicit_verilog);
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/* 5. Dump template for all the modules */
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if (TRUE == fpga_verilog_opts.print_user_defined_template) {
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print_verilog_submodule_templates(module_manager, Arch.spice->circuit_lib, std::string(verilog_dir), std::string(submodule_dir));
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}
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/* Create a header file to include all the subckts */
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vpr_printf(TIO_MESSAGE_INFO,
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"Generating header file for primitive modules...\n");
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print_verilog_netlist_include_header_file(netlist_names,
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submodule_dir,
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submodule_verilog_file_name);
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}
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