40 lines
1.6 KiB
Markdown
40 lines
1.6 KiB
Markdown
# Getting Started with FPGA-SPICE
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[](https://travis-ci.org/LNIS-Projects/OpenFPGA)
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[](https://openfpga.readthedocs.io/en/master/?badge=master)
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## Introduction
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FPGA-SPICE is an extension to VPR. It is an IP Verilog Generator allowing reliable and fast testing of heterogeneous architectures.
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## Compilation
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The different ways of compiling can be found in the **./compilation** folder.
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We currently implemented it for:
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1. Ubuntu 18.04
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2. Red Hat 7.5
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3. MacOS High Sierra 10.13.4
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Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.
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## Documentation
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OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) includes tutorials, descriptions of the design flow, and tool options.
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## Examples
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You can find in the folder **./examples**. This will help you get in touch with the software and test different configurations to see how FPGA-SPICE reacts to them.
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./example_x.sh allows to launch the script linked to example_x.xml and .blif.
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In all the examples, the CLBs are composed of LUTs, FFs and MUXs as a base.
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Example 1 shows a very basic design with only 4 inputs on the LUTs, a FF and a MUX in the CLB (only 1). It implements an inverter and allows the user to see the very core of the .xml file.
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Example 2 increases the complexity by having 3x3 CLBs and 4 slices per CLB. The slices provide a feedback to the input structure and input MUXs are added.
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