Go to file
tangxifan f5824ffc20
Merge pull request #600 from lnis-uofu/VPR_INTEGRATION
Fix a small typo to trigger the CI flow.
2022-03-23 08:33:38 +08:00
.github [FPGA-Verilog] Now port/wire names uses "__" to avoid collision with FPGA global ports 2022-03-16 20:51:37 +08:00
abc Add latest abc and update ace dependence 2019-05-03 18:56:03 -06:00
ace2 Now we use the ace from VTR 2019-07-16 17:00:09 -06:00
cmake copy missing cmake modules from vtr project 2020-01-03 21:57:19 -05:00
docker correct yosys paths for CI 2021-11-04 09:11:57 +05:30
docs Fix a small typo to trigger the CI flow. 2022-03-22 16:36:45 -07:00
libopenfpga fix openfpga_digest functions to work on WIN32(MinGW-w64-g++) as well as Linux 2022-03-17 22:05:30 +05:30
libs Include limits in argparse.cpp 2021-11-28 07:57:31 +01:00
openfpga [Engine] Now global port can be connected partial pins of a tile port 2022-03-20 11:36:03 +08:00
openfpga_flow [Script] Disable SDC writer in multiclock examples 2022-03-20 11:05:29 +08:00
vpr don't leave bus ports unconnected 2022-03-09 08:25:20 -08:00
yosys@dca8fb54aa [Github] Now use YosysHQ v0.10 release as a submodule 2021-10-29 14:19:26 -07:00
yosys-plugins@a2a80a1efb Bump yosys-plugins from `d849fd4` to `a2a80a1` 2022-03-21 06:32:35 +00:00
.dockerignore fixed missing yosys share directory 2021-12-02 00:05:17 -07:00
.gitignore Github action optimizations 2020-12-10 14:35:19 -07:00
.gitmodules update yosys-symbiflow-plugins to latest to fix quicklogic tests 2021-11-17 15:43:45 +05:30
.readthedocs.yml Support SVG in Sphinx Latex building (#220) 2021-02-07 18:53:16 -07:00
CMakeLists.txt Updated Patch Count 2022-03-22 00:02:06 +00:00
LICENSE Create LICENSE 2018-06-26 21:52:08 -07:00
Makefile Updating yosys-plugin compilation to create command synth_ql instead of synth_quicklogic. This is done to surpass the assertion failure 2021-11-12 01:46:06 -08:00
README.md Update README.md 2021-04-05 11:37:43 -06:00
openfpga.sh Fixing small typo in openfpga.sh 2021-10-11 13:52:31 +00:00
requirements.txt [Cleanup] Removed deadcode 2021-02-03 10:35:14 -07:00

README.md

Getting Started with OpenFPGA

linux build Documentation Status

Introduction

The award-winning OpenFPGA framework is the first open-source FPGA IP generator supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.

If this is the first time you learn OpenFPGA, we strongly recommend you to watch the introduction video about OpenFPGA

A quick overview of OpenFPGA tools can be found here. We also recommend potential users to checkout the summary of technical capabilities before compiling.

Compilation

A tutorial video about how-to-compile can be found here

Before start, we strongly recommend you to read the required dependencies at compilation guidelines. It also includes detailed information about docker image.


Compilation Steps:

# Clone the repository and go inside it
git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA
make all

Quick Compilation Verification

To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository.

python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs

Python3 and iVerilog v10.1+ are required. GUI will pop-up if enabled during compilation.


Supported Operating Systems

We currently target OpenFPGA for:

  1. Ubuntu 18.04
  2. Red Hat 7.5

The tool was tested with these operating systems. It might work with earlier versions and other distributions.

Documentation

OpenFPGA's full documentation includes tutorials, descriptions of the design flow, and tool options.

Tutorials

You can find a set of tutorials, with which you get familiar with the tool and use OpenFPGA in various purposes.