28 lines
906 B
XML
28 lines
906 B
XML
<config>
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<verilog_files>
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<!-- Way of specifying multiple files in a project -->
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<verilog_file>multiply72.v</verilog_file>
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</verilog_files>
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<output>
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<!-- These are the output flags for the project -->
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<output_type>blif_all_soft</output_type>
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<output_path_and_name>./multiply72.blif</output_path_and_name>
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<target>
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<!-- This is the target device the output is being built for -->
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<arch_file>fpga_arch_models.xml</arch_file>
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</target>
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</output>
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<optimizations>
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<!-- Options for hard multipliers: -->
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<!-- if size <= min then soft logic used -->
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<!-- if fixed == 1 then mults expanded to fixed hard block size -->
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<multiply min="3" fixed="1"/>
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</optimizations>
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<debug_outputs>
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<!-- Various debug options -->
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<debug_output_path>.</debug_output_path>
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<output_ast_graphs>1</output_ast_graphs>
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<output_netlist_graphs>1</output_netlist_graphs>
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</debug_outputs>
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</config>
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