33 lines
511 B
Verilog
33 lines
511 B
Verilog
///////////////////////////////
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// //
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// fifo_1bit benchmark //
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// //
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///////////////////////////////
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module fifo_1bit(
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rst,
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clk,
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data_in,
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data_out );
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input rst;
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input clk;
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input data_in;
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output data_out;
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reg[31:0] int_reg;
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assign data_out = int_reg[31];
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always@(posedge clk or posedge rst) begin
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if(rst) begin
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int_reg <= 32'h00;
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end
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else begin
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int_reg[0] <= data_in;
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int_reg[32:1] = int_reg[31:0];
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end
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end
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endmodule
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