OpenFPGA/openfpga_flow/tasks/basic_tests/global_tile_ports
tangxifan 5cb104a5f6 [test] fixed a bug 2024-07-08 22:04:40 -07:00
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global_tile_4clock/config [Test] Adapt pin constraints due to changes in pin names 2022-02-15 16:06:46 -08:00
global_tile_4clock_pin/config [Test] Add a test case to validate separated clock pins in global port 2022-03-20 11:02:07 +08:00
global_tile_clock/config [test] fixed some bugs 2024-05-07 11:23:33 -07:00
global_tile_clock_subtile/config [test] fixed a bug 2024-07-08 22:04:40 -07:00
global_tile_clock_subtile_port_merge/config [test] use a different W to avoid vvp collapse 2024-05-07 12:20:58 -07:00
global_tile_clock_subtile_port_merge_fabric_tile_group_config/config [core] fixed some bugs 2023-09-25 22:27:24 -07:00
global_tile_reset/config [script] now suggest to skip pb_pin_fixup step in example scripts for most test cases 2022-09-29 10:45:27 -07:00