OpenFPGA/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder
tangxifan bd37f0d542 correct bugs in decoder data port alignment to memory ports of multiplexing structure 2019-10-21 13:16:15 -06:00
..
build_decoder_modules.cpp add decoder module builders 2019-10-18 21:01:10 -06:00
build_decoder_modules.h add decoder module builders 2019-10-18 21:01:10 -06:00
build_essential_modules.cpp plug in MUX module graph generation, still local encoders contain dangling net, bug fixing 2019-10-21 00:00:30 -06:00
build_essential_modules.h plug in MUX module graph generation, still local encoders contain dangling net, bug fixing 2019-10-21 00:00:30 -06:00
build_module_graph.cpp plug in MUX module graph generation, still local encoders contain dangling net, bug fixing 2019-10-21 00:00:30 -06:00
build_module_graph.h add module builders for essential gates 2019-10-18 20:41:05 -06:00
build_mux_modules.cpp correct bugs in decoder data port alignment to memory ports of multiplexing structure 2019-10-21 13:16:15 -06:00
build_mux_modules.h plug in MUX module graph generation, still local encoders contain dangling net, bug fixing 2019-10-21 00:00:30 -06:00
build_top_module_directs.cpp start developing module graph builders 2019-10-18 20:02:02 -06:00
build_top_module_directs.h start developing module graph builders 2019-10-18 20:02:02 -06:00
build_top_module_memory.cpp start developing module graph builders 2019-10-18 20:02:02 -06:00
build_top_module_memory.h start developing module graph builders 2019-10-18 20:02:02 -06:00