48 lines
3.8 KiB
Markdown
48 lines
3.8 KiB
Markdown
# Naming convention for VPR architecture files
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Please reveal the following architecture features in the names to help quickly spot architecture files.
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- k<lut\_size>\_<frac><Native>: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size.
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* The keyword 'frac' is to specify if fracturable LUT is used or not.
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* The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch).
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- N<le\_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
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- tileable<IO|ConcatWire>: If the routing architecture is tileable or not.
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* The keyword 'IO' specifies if the I/O tile is tileable or not
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* The keyword 'ConcatWire' specifies if the routing wires can be continued in the same direction or not. For example, L4 -> L1
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- fracff<2edge>: Use multi-mode flip-flop model, where reset/set polarity is configurable. When 2edge is specified, clock polarity can be switched between postive edge triggered and negative edge triggered
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- adder\_chain: If hard adder/carry chain is used inside CLBs
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- register\_chain: If shift register chain is used inside CLBs
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- scan\_chain: If scan chain testing infrastructure is used inside CLBs
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- <wide>\_<frac>\_mem<mem\_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword 'wide' is to specify if the BRAM spans more than 1 column. The keyword 'frac' is to specify if the BRAM is fracturable to operate in different modes.
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- <wide>\_<frac>\_dsp<dsp\_size>reg: If Digital Signal Processor (DSP) is used or not. If used, the input size should be clarified here.
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- The keyword 'wide' is to specify if the DSP spans more than 1 column.
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- The keyword 'frac' is to specify if the DSP is fracturable to operate in different modes.
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- The keyword 'reg' is to specify if the DSP has input and output registers. If only input or output registers are used, the keyword will be 'regin' or 'regout' respectively.
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- mem<mem\_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword wide is to specify if the BRAM spanns more than 1 column.
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- aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
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- multi\_io\_capacity: If I/O capacity is different on each side of FPGAs.
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- reduced\_io: If I/Os only appear a certain or multiple sides of FPGAs
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- registerable\_io: If I/Os are registerable (can be either combinational or sequential)
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- IoSubtile: If I/O block contains sub tiles (more compact with a higher density of I/Os)
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- PerimeterCb: If connection blocks can occur on perimeter I/Os (I/O tile has more routability)
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- CustomIoLoc: Use OpenFPGA's extended custom I/O location syntax
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- rstOnLut: The reset signal of CLB can feed LUT inputs through a local routing architecture
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- localClkGen: The clock signal of CLB can be generated by internal programmable resources
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- localRstGen: The reset signal of CLB can be generated by internal programmable resources
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- <feature\_size>: The technology node which the delay numbers are extracted from.
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- TileOrgz<Type>: How tile is organized.
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* Top-left (Tl): the pins of a tile are placed on the top side and left side only
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* Top-right (Tr): the pins of a tile are placed on the top side and right side only
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* Bottom-right (Br): the pins of a tile are placed on the bottom side and right side only
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- GlobalTile<Int>Clk: How many clocks are defined through global ports from physical tiles. <Int> is the number of clocks
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- ecb: *Enhanced Connection Block* where connection blocks includes feedback connections
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Other features are used in naming should be listed here.
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# Update architecture files in batch
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## From v1.1 to v1.2
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```
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make v1p1_to_v1p2
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```
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