dd577e37e0
* BRAM preload data - generic way to extract data from design * Add docs and support special __layout__ case * Add test * Fix warning * Change none-fabric to non-fabric * LUTRAM Support Phase 1 * Add Test * Add more protocol checking to enable LUTRAM feature * Move the config setting under config protocol * Revert any changes --------- Co-authored-by: chungshien-chai <chungshien.chai@gmail.com> |
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.. | ||
basic_reg_test.sh | ||
basic_reg_yosys_only_test.sh | ||
fpga_bitstream_reg_test.sh | ||
fpga_sdc_reg_test.sh | ||
fpga_spice_reg_test.sh | ||
fpga_verilog_reg_test.sh | ||
iwls_benchmark_reg_test.sh | ||
micro_benchmark_reg_test.sh | ||
quicklogic_reg_test.sh | ||
tcl_reg_test.sh | ||
vtr_benchmark_reg_test.sh |