tangxifan 6122863548 [Test] Add a test case to validate the multi-shift-register-chain QL memory bank		2021-10-09 20:44:28 -07:00
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custom_fabric_netlist_location/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
fabric_key	[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key	2021-10-05 11:39:53 -07:00
fixed_device_support/config	[Test] Use proper template for some failing tests	2021-06-09 14:24:34 -06:00
fixed_simulation_settings	[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency	2021-10-06 12:12:15 -07:00
full_testbench	[Test] Add a test case to validate the multi-shift-register-chain QL memory bank	2021-10-09 20:44:28 -07:00
generate_fabric	[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification	2021-04-11 17:26:27 -06:00
generate_testbench/config	[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification	2021-04-11 17:26:27 -06:00
global_tile_ports	[Test] Update all the tasks that use counter benchmark	2021-07-02 17:29:13 -06:00
k4_series	[Test] Bug fix on the test case for multi-mode FF and pin constraints	2021-07-02 15:27:27 -06:00
preconfig_testbench	[Test] Added two cases to validate testbench generation without self checking	2021-06-29 16:06:15 -06:00
tile_organization	[Test] Add test case for tileable I/O	2020-12-04 16:02:47 -07:00