tangxifan bc9d95408e bug fixed and refactored intermediate buffer addition		2019-09-05 16:09:28 -06:00
..
base	implementing mux Verilog generation. Bugs detected, fixing ongoing	2019-09-04 23:54:53 -06:00
bitstream	replace spice_models with circuit model in bitstream generator	2019-08-16 16:36:49 -06:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
router	fixed bugs in configure pb_rr_graph and dependence on testbenches	2019-08-16 18:20:30 -06:00
shell	Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb	2019-05-13 14:45:57 -06:00
spice	added Switch Block SubType and SubFs for tileable rr_graph generation	2019-07-02 10:00:02 -06:00
verilog	bug fixed and refactored intermediate buffer addition	2019-09-05 16:09:28 -06:00