192 lines
7.9 KiB
C++
192 lines
7.9 KiB
C++
/********************************************************************
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* This file includes functions to read an OpenFPGA architecture file
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* which are built on the libarchopenfpga library
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_time.h"
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from openfpgashell library */
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#include "command_exit_codes.h"
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/* Headers from vpr library */
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#include "read_activity.h"
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#include "vpr_device_annotation.h"
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#include "pb_type_utils.h"
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#include "annotate_physical_tiles.h"
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#include "annotate_pb_types.h"
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#include "annotate_pb_graph.h"
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#include "annotate_routing.h"
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#include "annotate_rr_graph.h"
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#include "annotate_simulation_setting.h"
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#include "annotate_bitstream_setting.h"
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#include "mux_library_builder.h"
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#include "build_tile_direct.h"
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#include "annotate_placement.h"
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#include "openfpga_link_arch.h"
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/* Include global variables of VPR */
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#include "globals.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* A function to identify if the routing resource graph generated by
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* VPR is support by OpenFPGA
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* - Currently we only support uni-directional
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* It means every routing tracks must have a direction
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*******************************************************************/
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static
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bool is_vpr_rr_graph_supported(const RRGraph& rr_graph) {
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/* Check if the rr_graph is uni-directional*/
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for (const RRNodeId& node : rr_graph.nodes()) {
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if (CHANX != rr_graph.node_type(node) && CHANY != rr_graph.node_type(node)) {
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continue;
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}
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if (BI_DIRECTION == rr_graph.node_direction(node)) {
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VTR_LOG_ERROR("Routing resource graph is bi-directional. OpenFPGA currently supports uni-directional routing architecture only.\n");
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return false;
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}
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}
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return true;
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}
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/********************************************************************
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* Top-level function to link openfpga architecture to VPR, including:
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* - physical pb_type
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* - mode selection bits for pb_type and pb interconnect
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* - circuit models for pb_type and pb interconnect
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* - physical pb_graph nodes and pb_graph pins
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* - circuit models for global routing architecture
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*******************************************************************/
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int link_arch(OpenfpgaContext& openfpga_ctx,
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const Command& cmd, const CommandContext& cmd_context) {
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vtr::ScopedStartFinishTimer timer("Link OpenFPGA architecture to VPR architecture");
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CommandOptionId opt_activity_file = cmd.option("activity_file");
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CommandOptionId opt_sort_edge = cmd.option("sort_gsb_chan_node_in_edges");
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CommandOptionId opt_verbose = cmd.option("verbose");
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/* Build fast look-up between physical tile pin index and port information */
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build_physical_tile_pin2port_info(g_vpr_ctx.device(),
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openfpga_ctx.mutable_vpr_device_annotation());
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/* Annotate pb_type graphs
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* - physical pb_type
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* - mode selection bits for pb_type and pb interconnect
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* - circuit models for pb_type and pb interconnect
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*/
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annotate_pb_types(g_vpr_ctx.device(), openfpga_ctx.arch(),
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openfpga_ctx.mutable_vpr_device_annotation(),
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cmd_context.option_enable(cmd, opt_verbose));
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/* Annotate pb_graph_nodes
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* - Give unique index to each node in the same type
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* - Bind operating pb_graph_node to their physical pb_graph_node
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* - Bind pins from operating pb_graph_node to their physical pb_graph_node pins
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*/
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annotate_pb_graph(g_vpr_ctx.device(),
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openfpga_ctx.mutable_vpr_device_annotation(),
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cmd_context.option_enable(cmd, opt_verbose));
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/* Annotate routing architecture to circuit library */
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annotate_rr_graph_circuit_models(g_vpr_ctx.device(),
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openfpga_ctx.arch(),
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openfpga_ctx.mutable_vpr_device_annotation(),
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cmd_context.option_enable(cmd, opt_verbose));
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/* Annotate routing results:
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* - net mapping to each rr_node
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* - previous nodes driving each rr_node
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*/
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openfpga_ctx.mutable_vpr_routing_annotation().init(g_vpr_ctx.device().rr_graph);
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annotate_rr_node_nets(g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.routing(),
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openfpga_ctx.mutable_vpr_routing_annotation(),
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cmd_context.option_enable(cmd, opt_verbose));
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annotate_rr_node_previous_nodes(g_vpr_ctx.device(), g_vpr_ctx.clustering(), g_vpr_ctx.routing(),
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openfpga_ctx.mutable_vpr_routing_annotation(),
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cmd_context.option_enable(cmd, opt_verbose));
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/* Build the routing graph annotation
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* - RRGSB
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* - DeviceRRGSB
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*/
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if (false == is_vpr_rr_graph_supported(g_vpr_ctx.device().rr_graph)) {
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return CMD_EXEC_FATAL_ERROR;
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}
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annotate_device_rr_gsb(g_vpr_ctx.device(),
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openfpga_ctx.mutable_device_rr_gsb(),
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cmd_context.option_enable(cmd, opt_verbose));
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if (true == cmd_context.option_enable(cmd, opt_sort_edge)) {
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sort_device_rr_gsb_chan_node_in_edges(g_vpr_ctx.device().rr_graph,
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openfpga_ctx.mutable_device_rr_gsb(),
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cmd_context.option_enable(cmd, opt_verbose));
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}
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/* Build multiplexer library */
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openfpga_ctx.mutable_mux_lib() = build_device_mux_library(g_vpr_ctx.device(),
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const_cast<const OpenfpgaContext&>(openfpga_ctx));
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/* Build tile direct annotation */
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openfpga_ctx.mutable_tile_direct() = build_device_tile_direct(g_vpr_ctx.device(),
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openfpga_ctx.arch().arch_direct,
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cmd_context.option_enable(cmd, opt_verbose));
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/* Annotate placement results */
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annotate_mapped_blocks(g_vpr_ctx.device(),
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g_vpr_ctx.clustering(),
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g_vpr_ctx.placement(),
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openfpga_ctx.mutable_vpr_placement_annotation());
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/* Read activity file is manadatory in the following flow-run settings
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* - When users specify that number of clock cycles
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* should be inferred from FPGA implmentation
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* - When FPGA-SPICE is enabled
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*/
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std::unordered_map<AtomNetId, t_net_power> net_activity;
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if (true == cmd_context.option_enable(cmd, opt_activity_file)) {
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net_activity = read_activity(g_vpr_ctx.atom().nlist,
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cmd_context.option_value(cmd, opt_activity_file).c_str());
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}
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/* TODO: Annotate the number of clock cycles and clock frequency by following VPR results
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* We SHOULD create a new simulation setting for OpenFPGA use only
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* Avoid overwrite the raw data achieved when parsing!!!
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*/
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/* OVERWRITE the simulation setting in openfpga context from the arch
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* TODO: This will be removed when openfpga flow is updated
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*/
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//openfpga_ctx.mutable_simulation_setting() = openfpga_ctx.mutable_arch().sim_setting;
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if (CMD_EXEC_FATAL_ERROR == annotate_simulation_setting(g_vpr_ctx.atom(),
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net_activity,
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openfpga_ctx.mutable_simulation_setting())) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* Build bitstream annotation based on bitstream settings */
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if (CMD_EXEC_FATAL_ERROR == annotate_bitstream_setting(openfpga_ctx.bitstream_setting(),
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g_vpr_ctx.device(),
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openfpga_ctx.vpr_device_annotation(),
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openfpga_ctx.mutable_vpr_bitstream_annotation())) {
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return CMD_EXEC_FATAL_ERROR;
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}
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/* TODO: should identify the error code from internal function execution */
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return CMD_EXEC_SUCCESS;
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}
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} /* end namespace openfpga */
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