tangxifan cf34339e96 adapt essential gates for submodule generation		2020-02-16 11:57:19 -07:00
..
src	adapt essential gates for submodule generation	2020-02-16 11:57:19 -07:00
test_blif	use a micro benchmark for vpr quick-run	2020-01-26 17:56:22 -07:00
test_openfpga_arch	add lut module builder	2020-02-12 19:52:41 -07:00
test_script	bring fpga verilog create directory online	2020-02-15 20:38:45 -07:00
test_vpr_arch	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
CMakeLists.txt	start implement openfpga shell and use vpr as a macro	2020-01-22 20:20:10 -07:00