201 lines
8.7 KiB
C++
201 lines
8.7 KiB
C++
/******************************************************************************
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* This files includes declarations for most utilized functions
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* for data structures for module management.
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******************************************************************************/
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#ifndef MODULE_MANAGER_UTILS_H
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#define MODULE_MANAGER_UTILS_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <tuple>
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#include <vector>
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/* Headers from readarch library */
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#include "physical_types.h"
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/* Headers from openfpgautil library */
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#include "openfpga_port.h"
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/* Headers from readarchopenfpga library */
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#include "circuit_library.h"
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#include "circuit_types.h"
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#include "config_protocol.h"
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#include "decoder_library.h"
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#include "fabric_key.h"
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#include "module_manager.h"
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#include "vpr_device_annotation.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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constexpr std::array<ModuleManager::e_module_port_type, 3>
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MODULE_IO_PORT_TYPES = {ModuleManager::MODULE_GPIN_PORT,
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ModuleManager::MODULE_GPOUT_PORT,
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ModuleManager::MODULE_GPIO_PORT};
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void reserve_module_manager_module_nets(ModuleManager& module_manager,
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const ModuleId& module);
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size_t count_module_manager_module_configurable_children(
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const ModuleManager& module_manager, const ModuleId& module,
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const ModuleManager::e_config_child_type& config_child_type);
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std::pair<ModuleId, size_t> find_module_manager_instance_module_info(
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const ModuleManager& module_manager, const ModuleId& parent,
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const std::string& instance_name);
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ModuleId add_circuit_model_to_module_manager(
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ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model, const std::string& module_name);
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ModuleId add_circuit_model_to_module_manager(
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ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model);
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void add_reserved_sram_ports_to_module_manager(ModuleManager& module_manager,
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const ModuleId& module_id,
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const size_t& port_size);
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void add_formal_verification_sram_ports_to_module_manager(
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ModuleManager& module_manager, const ModuleId& module_id,
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const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
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const std::string& preproc_flag, const size_t& port_size);
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void add_sram_ports_to_module_manager(
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ModuleManager& module_manager, const ModuleId& module_id,
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const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
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const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits);
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void add_pb_sram_ports_to_module_manager(
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ModuleManager& module_manager, const ModuleId& module_id,
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const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
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const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits,
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const uint32_t defined_num_wl = 0);
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void add_primitive_pb_type_ports_to_module_manager(
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ModuleManager& module_manager, const ModuleId& module_id,
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t_pb_type* cur_pb_type, const VprDeviceAnnotation& vpr_device_annotation);
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void add_pb_type_ports_to_module_manager(ModuleManager& module_manager,
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const ModuleId& module_id,
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t_pb_type* cur_pb_type);
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bool module_net_is_local_wire(const ModuleManager& module_manager,
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const ModuleId& module_id,
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const ModuleNetId& module_net);
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bool module_net_include_output_short_connection(
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const ModuleManager& module_manager, const ModuleId& module_id,
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const ModuleNetId& module_net);
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bool module_net_include_local_short_connection(
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const ModuleManager& module_manager, const ModuleId& module_id,
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const ModuleNetId& module_net);
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void add_primitive_pb_type_module_nets(
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ModuleManager& module_manager, const ModuleId& pb_type_module,
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const ModuleId& child_module, const size_t& child_instance_id,
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const CircuitLibrary& circuit_lib, t_pb_type* cur_pb_type,
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const VprDeviceAnnotation& vpr_device_annotation);
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void add_module_nets_between_logic_and_memory_sram_bus(
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ModuleManager& module_manager, const ModuleId& parent_module,
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const ModuleId& logic_module, const size_t& logic_instance_id,
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const ModuleId& memory_module, const size_t& memory_instance_id,
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const CircuitLibrary& circuit_lib, const CircuitModelId& logic_model);
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void add_module_nets_cmos_flatten_memory_config_bus(
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ModuleManager& module_manager, const ModuleId& parent_module,
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const e_config_protocol_type& sram_orgz_type,
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const e_circuit_model_port_type& config_port_type,
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const ModuleManager::e_config_child_type& config_child_type);
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void add_module_nets_cmos_memory_bank_bl_config_bus(
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ModuleManager& module_manager, const ModuleId& parent_module,
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const e_config_protocol_type& sram_orgz_type,
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const e_circuit_model_port_type& config_port_type,
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const ModuleManager::e_config_child_type& config_child_type);
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void add_module_nets_cmos_memory_bank_wl_config_bus(
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ModuleManager& module_manager, const ModuleId& parent_module,
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const e_config_protocol_type& sram_orgz_type,
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const e_circuit_model_port_type& config_port_type,
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const ModuleManager::e_config_child_type& config_child_type);
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void add_module_nets_cmos_memory_chain_config_bus(
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ModuleManager& module_manager, const ModuleId& parent_module,
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const e_config_protocol_type& sram_orgz_type,
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const ModuleManager::e_config_child_type& config_child_type);
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void add_module_nets_cmos_memory_frame_config_bus(
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ModuleManager& module_manager, DecoderLibrary& decoder_lib,
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const ModuleId& parent_module,
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const ModuleManager::e_config_child_type& config_child_type);
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void add_module_nets_memory_config_bus(
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ModuleManager& module_manager, DecoderLibrary& decoder_lib,
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const ModuleId& parent_module, const e_config_protocol_type& sram_orgz_type,
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const e_circuit_model_design_tech& mem_tech,
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const ModuleManager::e_config_child_type& config_child_type);
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void add_pb_module_nets_memory_config_bus(
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ModuleManager& module_manager, DecoderLibrary& decoder_lib,
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const ModuleId& parent_module, const e_config_protocol_type& sram_orgz_type,
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const e_circuit_model_design_tech& mem_tech,
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const ModuleManager::e_config_child_type& config_child_type);
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size_t find_module_num_shared_config_bits(const ModuleManager& module_manager,
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const ModuleId& module_id);
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size_t find_module_num_config_bits(
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const ModuleManager& module_manager, const ModuleId& module_id,
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const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
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const e_config_protocol_type& sram_orgz_type);
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void add_module_global_input_ports_from_child_modules(
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ModuleManager& module_manager, const ModuleId& module_id,
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const std::vector<std::string>& port_name_to_ignore =
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std::vector<std::string>());
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void add_module_global_output_ports_from_child_modules(
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ModuleManager& module_manager, const ModuleId& module_id);
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void add_module_global_ports_from_child_modules(
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ModuleManager& module_manager, const ModuleId& module_id,
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const std::vector<std::string>& port_name_to_ignore =
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std::vector<std::string>());
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void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager,
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const ModuleId& module_id);
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size_t find_module_num_shared_config_bits_from_child_modules(
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ModuleManager& module_manager, const ModuleId& module_id);
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size_t find_module_num_config_bits_from_child_modules(
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ModuleManager& module_manager, const ModuleId& module_id,
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const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
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const e_config_protocol_type& sram_orgz_type,
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const ModuleManager::e_config_child_type& config_child_type);
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ModuleNetId create_module_source_pin_net(ModuleManager& module_manager,
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const ModuleId& cur_module_id,
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const ModuleId& src_module_id,
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const size_t& src_instance_id,
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const ModulePortId& src_module_port_id,
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const size_t& src_pin_id);
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void add_module_bus_nets(
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ModuleManager& module_manager, const ModuleId& cur_module_id,
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const ModuleId& src_module_id, const size_t& src_instance_id,
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const ModulePortId& src_module_port_id, const ModuleId& des_module_id,
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const size_t& des_instance_id, const ModulePortId& des_module_port_id);
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} /* end namespace openfpga */
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#endif
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