Baudouin Chauviere c7e1f7d90b Added explicit_verilog to regression test in a clean way		2019-10-03 10:17:04 -06:00
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SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
arch	Add testcase in regression test for architecture with 1 IO cell/IO block	2019-09-20 10:27:26 -06:00
benchmarks	Added Test Modes - Added blif VPR Option	2019-08-22 17:00:59 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
misc	Separated Modelsim tcl script generation	2019-09-07 12:36:22 -04:00
scripts	Added remove run directory option	2019-09-21 23:35:56 -06:00
tasks	Added explicit_verilog to regression test in a clean way	2019-10-03 10:17:04 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00