99 lines
4.1 KiB
C++
99 lines
4.1 KiB
C++
/*********************************************************************
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* This file includes top-level function to generate Verilog primitive modules
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* and print them to files
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********************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "verilog_submodule_utils.h"
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#include "verilog_essential_gates.h"
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#include "verilog_decoders.h"
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#include "verilog_mux.h"
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#include "verilog_lut.h"
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#include "verilog_wire.h"
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#include "verilog_memory.h"
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#include "verilog_writer_utils.h"
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#include "verilog_constants.h"
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#include "verilog_submodule.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/*********************************************************************
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* Top-level function to generate primitive modules:
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* 1. Logic gates: AND/OR, inverter, buffer and transmission-gate/pass-transistor
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* 2. Routing multiplexers
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* 3. Local encoders for routing multiplexers
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* 4. Wires
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* 5. Configuration memory blocks
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* 6. Verilog template
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********************************************************************/
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void print_verilog_submodule(ModuleManager& module_manager,
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NetlistManager& netlist_manager,
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const MuxLibrary& mux_lib,
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const CircuitLibrary& circuit_lib,
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const std::string& submodule_dir,
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const FabricVerilogOption& fpga_verilog_opts) {
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/* Register all the user-defined modules in the module manager
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* This should be done prior to other steps in this function,
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* because they will be instanciated by other primitive modules
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*/
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//add_user_defined_verilog_modules(module_manager, circuit_lib);
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print_verilog_submodule_essentials(const_cast<const ModuleManager&>(module_manager),
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netlist_manager,
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submodule_dir,
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circuit_lib);
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/* Routing multiplexers */
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/* NOTE: local decoders generation must go before the MUX generation!!!
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* because local decoders modules will be instanciated in the MUX modules
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*/
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print_verilog_submodule_mux_local_decoders(const_cast<const ModuleManager&>(module_manager),
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netlist_manager,
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mux_lib, circuit_lib,
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submodule_dir);
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print_verilog_submodule_muxes(module_manager, netlist_manager, mux_lib, circuit_lib,
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submodule_dir,
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fpga_verilog_opts.explicit_port_mapping());
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/* LUTes */
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print_verilog_submodule_luts(const_cast<const ModuleManager&>(module_manager),
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netlist_manager, circuit_lib,
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submodule_dir,
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fpga_verilog_opts.explicit_port_mapping());
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/* Hard wires */
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print_verilog_submodule_wires(const_cast<const ModuleManager&>(module_manager),
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netlist_manager, circuit_lib,
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submodule_dir);
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/* 4. Memories */
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print_verilog_submodule_memories(const_cast<const ModuleManager&>(module_manager),
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netlist_manager,
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mux_lib, circuit_lib,
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submodule_dir,
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fpga_verilog_opts.explicit_port_mapping());
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/* 5. Dump template for all the modules */
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if (true == fpga_verilog_opts.print_user_defined_template()) {
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print_verilog_submodule_templates(const_cast<const ModuleManager&>(module_manager),
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circuit_lib,
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submodule_dir);
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}
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/* Create a header file to include all the subckts */
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/*
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print_verilog_netlist_include_header_file(netlist_manager,
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submodule_dir.c_str(),
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SUBMODULE_VERILOG_FILE_NAME);
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*/
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}
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} /* end namespace openfpga */
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