tangxifan bba476fef4 add explicit port mapping support to Verilog testbench generator		2020-06-11 19:31:07 -06:00
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annotation	critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results	2020-04-18 21:04:46 -06:00
base	add explicit port mapping support to Verilog testbench generator	2020-06-11 19:31:07 -06:00
fabric	use constant string for inverted port naming	2020-06-11 19:31:07 -06:00
fpga_bitstream	add fabric bitstream writer	2020-04-21 12:02:10 -06:00
fpga_sdc	use constant string for inverted port naming	2020-06-11 19:31:07 -06:00
fpga_verilog	add explicit port mapping support to Verilog testbench generator	2020-06-11 19:31:07 -06:00
mux_lib	bug fix in lut and mux module generation on supporting spypads	2020-04-22 14:41:16 -06:00
repack	Critical patch on repacking about wire LUT support.	2020-04-19 16:42:31 -06:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	use constant string for inverted port naming	2020-06-11 19:31:07 -06:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	fix memory leakage in openfpga title	2020-04-07 16:14:41 -06:00