tangxifan 509f5eb6dc [doc] add documentation about clock network description file		2023-04-20 17:06:53 +08:00
..
figures	[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank	2021-10-04 12:09:42 -07:00
addon_vpr_syntax.rst	[doc] update doc with the new xml syntax	2022-09-08 17:00:16 -07:00
annotate_vpr_arch.rst	[doc] add documentation about clock network description file	2023-04-20 17:06:53 +08:00
circuit_library.rst	[Doc] More explanantion on the use of config_enable attribute for circuit ports	2022-02-23 15:53:58 -08:00
circuit_model_examples.rst	fix mux syntax in circuit_model_examples	2023-02-10 10:22:37 -07:00
config_protocol.rst	[doc] fixed bugs on small figure sizes shown	2022-12-06 17:20:46 -08:00
direct_interconnect.rst	clean-up documentation for a shallow hierarchy	2020-06-11 19:31:08 -06:00
fabric_key.rst	[Doc] Group file format documentation into a unified section	2021-01-19 19:44:44 -07:00
generality.rst	remove obselete vpr7 XML syntax from documentation	2020-07-15 11:13:47 -06:00
index.rst	add documentation for fabric key and reorganize command references	2020-06-12 16:15:16 -06:00
simulation_setting.rst	[Doc] Update documentation about the clock definition for programming clocks in simulation settings	2021-10-06 13:50:33 -07:00
technology_library.rst	update documentation about new XML syntax max width	2020-07-24 16:33:01 -06:00