89 lines
1.8 KiB
Verilog
89 lines
1.8 KiB
Verilog
//-----------------------------------------------------
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// Design Name : testbench for static_dff
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// File Name : ff_tb.v
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// Function : D flip-flop with asyn reset and set
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// Coder : Xifan TANG
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//-----------------------------------------------------
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//----- Time scale: simulation time step and accuracy -----
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`timescale 1ns / 1ps
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module sram6T_rram_tb;
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// voltage sources
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wire read;
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wire nequalize;
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wire din;
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wire dout;
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wire doutb;
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reg [0:2] bl;
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reg [0:2] wl;
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reg prog_clock;
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// Parameters
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parameter prog_clk_period = 2; // [ns] a full clock period
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// Unit Under Test
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sram6T_rram U0 (read, nequalize, din, dout, doutb, bl, wl);
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// Voltage stimuli
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// read : alway disabled
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assign read = 1'b0;
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// nequalize: always disabled
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assign nequalize = 1'b1;
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// din: always disabled
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assign din = 1'b0;
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// Programming clock
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initial
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begin
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prog_clock = 1'b0;
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end
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always
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begin
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#prog_clk_period prog_clock = ~prog_clock;
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end
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// Task: assign BL and WL values
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task prog_blwl;
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input [0:2] bl_val;
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input [0:2] wl_val;
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begin
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@(posedge prog_clock);
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bl = bl_val;
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wl = wl_val;
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end
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endtask
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// Test two cases:
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// 1. Program dout to 0
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// bl[0] = 1, wl[2] = 1
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// bl[2] = 1, wl[0] = 1
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// 2. Program dout to 1
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// bl[1] = 1, wl[2] = 1
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// bl[2] = 1, wl[1] = 1
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initial
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begin
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bl = 3'b000;
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wl = 3'b000;
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// 1. Program dout to 0
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// bl[0] = 1, wl[2] = 1
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prog_blwl(3'b100, 3'b001);
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// bl[2] = 1, wl[0] = 1
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prog_blwl(3'b001, 3'b100);
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// 2. Program dout to 1
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// bl[1] = 1, wl[2] = 1
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prog_blwl(3'b010, 3'b001);
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// bl[2] = 1, wl[1] = 1
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prog_blwl(3'b100, 3'b010);
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// 3. Program dout to 0
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// bl[0] = 1, wl[2] = 1
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prog_blwl(3'b100, 3'b001);
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// bl[2] = 1, wl[0] = 1
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prog_blwl(3'b001, 3'b100);
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end
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// Outputs are wired to dout and doutb
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endmodule
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