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OpenFPGA/openfpga_flow/openfpga_cell_library
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tangxifan 5eb04e6fff [HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals 2020-11-22 20:53:32 -07:00
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spice [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
spice_testbench [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
verilog [HDL] Correct bugs in MUX2 standard cell where iverilog has problems in deposit initial signals 2020-11-22 20:53:32 -07:00
verilog_testbench [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00