60 lines
1.8 KiB
Verilog
60 lines
1.8 KiB
Verilog
//-----------------------------------------------------
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// Design Name : General Purpose I/Os
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// File Name : gpio.v
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// Coder : Xifan TANG
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//-----------------------------------------------------
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//-----------------------------------------------------
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// Function : A minimum general purpose I/O
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//-----------------------------------------------------
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module GPIO (
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input A, // Data output
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output Y, // Data input
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inout PAD, // bi-directional pad
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input DIR // direction control
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);
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//----- when direction enabled, the signal is propagated from PAD to data input
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assign Y = DIR ? PAD : 1'bz;
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//----- when direction is disabled, the signal is propagated from data out to pad
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assign PAD = DIR ? 1'bz : A;
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endmodule
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//-----------------------------------------------------
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// Function : A minimum input pad
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//-----------------------------------------------------
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module GPIN (
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inout A, // External PAD signal
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output Y // Data input
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);
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assign Y = A;
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endmodule
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//-----------------------------------------------------
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// Function : A minimum output pad
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//-----------------------------------------------------
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module GPOUT (
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inout Y, // External PAD signal
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input A // Data output
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);
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assign Y = A;
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endmodule
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//-----------------------------------------------------
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// Function : A minimum embedded I/O
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// just an overlay to interface other components
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//-----------------------------------------------------
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module EMBEDDED_IO (
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input SOC_IN, // Input to drive the inpad signal
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output SOC_OUT, // Output the outpad signal
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output SOC_DIR, // Output the directionality
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output FPGA_IN, // Input data to FPGA
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input FPGA_OUT, // Output data from FPGA
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input FPGA_DIR // direction control
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);
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assign FPGA_IN = SOC_IN;
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assign SOC_OUT = FPGA_OUT;
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assign SOC_DIR = FPGA_DIR;
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endmodule
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