tangxifan bc47b3ca94 update verilog module writer to the global spy ports		2020-04-05 16:04:13 -06:00
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src	update verilog module writer to the global spy ports	2020-04-05 16:04:13 -06:00
test_blif	add missing files for micro benchmarks	2020-03-20 11:08:55 -06:00
test_openfpga_arch	add test openfpga arch XML with spy pad	2020-04-05 15:23:07 -06:00
test_script	add testing script for the spy io	2020-04-05 15:24:40 -06:00
test_vpr_arch	added FPGA architecture with I/Os on the left and right sides	2020-04-01 15:46:38 -06:00
CMakeLists.txt	add simulation ini file writer	2020-02-27 18:01:47 -07:00