tangxifan 7c6e000be8 [Tool] bug fix		2021-04-10 15:36:02 -06:00
..
annotation	Merge branch 'master' into netlist_name_patch	2021-03-15 10:06:24 -06:00
base	[Tool] Change routing module port naming to include architecture port names	2021-03-14 19:35:49 -06:00
fabric	[Tool] Change routing module port naming to include architecture port names	2021-03-14 19:35:49 -06:00
fpga_bitstream	[Tool] bug fix	2021-04-10 15:36:02 -06:00
fpga_sdc	[Tool] Change routing module port naming to include architecture port names	2021-03-14 19:35:49 -06:00
fpga_spice	[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming	2020-12-05 12:44:09 -07:00
fpga_verilog	[Tool] Capsulate fabric bitstream organization for configuration chain	2021-04-10 14:28:31 -06:00
mux_lib	[Tool] Support superLUT circuit model in core engine	2021-02-09 20:23:05 -07:00
repack	[Tool] Extend bitstream setting to support mode bits overload from eblif file	2021-03-10 20:45:48 -07:00
tile_direct	bug fixed in tile direct builder	2020-03-21 12:43:56 -06:00
utils	[Tool] Capsulate fabric bitstream organization for configuration chain	2021-04-10 14:28:31 -06:00
vpr_wrapper	add rr_segment binding to circuit model	2020-02-12 11:21:40 -07:00
ctag_src.sh	add ctags script to index openfpga source files	2020-01-24 10:15:16 -07:00
main.cpp	[Tool] Add --version to openfpga shell option and a command to openfpga shell	2021-01-27 16:03:46 -07:00