tangxifan a6186db315 [Test] Update bitstream annotation with new syntax		2021-03-10 20:45:17 -07:00
..
counter_5clock_test/config	Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification	2021-03-07 22:25:01 -08:00
flow_test/config	Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS	2021-03-07 22:02:11 -08:00
lut_adder_test/config	[Test] Update bitstream annotation with new syntax	2021-03-10 20:45:17 -07:00
sdc_controller_test/config	Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys	2021-02-25 23:39:07 -08:00