OpenFPGA/openfpga_flow/tasks/fpga_verilog
tangxifan b90a17543d [Test] Add new test case to test default nettype in different verilog syntax 2021-02-28 16:16:45 -07:00
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adder [Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file 2021-02-04 20:20:10 -07:00
bram [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
depopulate_crossbar/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
duplicated_grid_pin/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
fabric_chain [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
flatten_routing/config [Test] Deploy default net type option to test case 2021-02-28 12:20:43 -07:00
fully_connected_output_crossbar/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
io [Test] Update test case to use new shell script 2021-01-10 11:09:10 -07:00
lut_design [Test] Update test case to use dedicated eblif file 2021-02-09 15:51:57 -07:00
mux_design [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
power_gated_design/power_gated_inverter/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
spypad/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
thru_channel [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
untileable/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
verilog_netlist_formats [Test] Add new test case to test default nettype in different verilog syntax 2021-02-28 16:16:45 -07:00