141 lines
7.0 KiB
C++
141 lines
7.0 KiB
C++
/********************************************************************
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* Add commands to the OpenFPGA shell interface,
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* in purpose of generate Verilog netlists modeling the full FPGA fabric
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* This is one of the core engine of openfpga, including:
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* - generate_fabric_verilog : generate Verilog netlists about FPGA fabric
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* - generate_fabric_verilog_testbench : TODO: generate Verilog testbenches
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*******************************************************************/
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#include "openfpga_verilog.h"
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#include "openfpga_verilog_command.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* - Add a command to Shell environment: generate fabric Verilog
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* - Add associated options
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* - Add command dependency
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*******************************************************************/
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static
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ShellCommandId add_openfpga_write_fabric_verilog_command(openfpga::Shell<OpenfpgaContext>& shell,
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const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds) {
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Command shell_cmd("write_fabric_verilog");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory for Verilog netlists");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* Add an option '--explicit_port_mapping' */
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shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
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/* Add an option '--include_timing' */
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shell_cmd.add_option("include_timing", false, "Enable timing annotation in Verilog netlists");
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/* Add an option '--include_signal_init' */
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shell_cmd.add_option("include_signal_init", false, "Initialize all the signals in Verilog netlists");
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/* Add an option '--support_icarus_simulator' */
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shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog netlists to support icarus simulator");
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/* Add an option '--print_user_defined_template' */
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shell_cmd.add_option("print_user_defined_template", false, "Generate a template Verilog files for user-defined circuit models");
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/* Add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "Enable verbose output");
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/* Add command 'write_fabric_verilog' to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate Verilog netlists modeling full FPGA fabric");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_fabric_verilog);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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/********************************************************************
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* - Add a command to Shell environment: write Verilog testbench
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* - Add associated options
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* - Add command dependency
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*******************************************************************/
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static
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ShellCommandId add_openfpga_write_verilog_testbench_command(openfpga::Shell<OpenfpgaContext>& shell,
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const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds) {
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Command shell_cmd("write_verilog_testbench");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option("file", true, "Specify the output directory for Verilog netlists");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* Add an option '--reference_benchmark_file_path'*/
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CommandOptionId ref_bm_opt = shell_cmd.add_option("reference_benchmark_file_path", true, "Specify the file path to the reference Verilog netlist");
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shell_cmd.set_option_require_value(ref_bm_opt, openfpga::OPT_STRING);
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/* Add an option '--print_top_testbench' */
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shell_cmd.add_option("print_top_testbench", false, "Generate a full testbench for top-level fabric module with autocheck capability");
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/* Add an option '--fast_configuration' */
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shell_cmd.add_option("fast_configuration", false, "Reduce the period of configuration by skip zero data points");
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/* Add an option '--print_formal_verification_top_netlist' */
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shell_cmd.add_option("print_formal_verification_top_netlist", false, "Generate a top-level module which can be used in formal verification");
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/* Add an option '--print_preconfig_top_testbench' */
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shell_cmd.add_option("print_preconfig_top_testbench", false, "Generate a pre-configured testbench for top-level fabric module with autocheck capability");
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/* Add an option '--print_simulation_ini' */
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CommandOptionId sim_ini_opt = shell_cmd.add_option("print_simulation_ini", false, "Generate a .ini file as an exchangeable file to enable HDL simulations");
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shell_cmd.set_option_require_value(sim_ini_opt, openfpga::OPT_STRING);
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/* Add an option '--explicit_port_mapping' */
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shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
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/* Add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "Enable verbose output");
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/* Add command to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(shell_cmd, "generate Verilog testbenches for full FPGA fabric");
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, write_verilog_testbench);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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void add_openfpga_verilog_commands(openfpga::Shell<OpenfpgaContext>& shell) {
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/* Get the unique id of 'build_fabric' command which is to be used in creating the dependency graph */
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const ShellCommandId& build_fabric_cmd_id = shell.command(std::string("build_fabric"));
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/* Add a new class of commands */
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ShellCommandClassId openfpga_verilog_cmd_class = shell.add_command_class("FPGA-Verilog");
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/********************************
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* Command 'write_fabric_verilog'
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*/
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/* The 'write_fabric_verilog' command should NOT be executed before 'build_fabric' */
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std::vector<ShellCommandId> fabric_verilog_dependent_cmds;
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fabric_verilog_dependent_cmds.push_back(build_fabric_cmd_id);
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add_openfpga_write_fabric_verilog_command(shell,
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openfpga_verilog_cmd_class,
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fabric_verilog_dependent_cmds);
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/********************************
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* Command 'write_verilog_testbench'
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*/
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/* The command 'write_verilog_testbench' should NOT be executed before 'build_fabric' */
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std::vector<ShellCommandId> verilog_testbench_dependent_cmds;
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verilog_testbench_dependent_cmds.push_back(build_fabric_cmd_id);
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add_openfpga_write_verilog_testbench_command(shell,
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openfpga_verilog_cmd_class,
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verilog_testbench_dependent_cmds);
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}
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} /* end namespace openfpga */
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