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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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b80e26e711
OpenFPGA
/
openfpga
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tangxifan
b80e26e711
update bitstream generator to use sorted edges
2020-03-08 15:36:47 -06:00
..
src
update bitstream generator to use sorted edges
2020-03-08 15:36:47 -06:00
test_blif
start debugging with micro benchmarks. Spot problem in local routing
2020-02-28 15:41:32 -07:00
test_openfpga_arch
bug fixed for io location mapping
2020-02-28 14:46:01 -07:00
test_script
put analysis sdc writer online. Minor bug in redudant '/' to be fixed
2020-03-02 19:54:18 -07:00
test_vpr_arch
tileable rr_graph builder ready to debug
2020-03-06 16:18:45 -07:00
CMakeLists.txt
add simulation ini file writer
2020-02-27 18:01:47 -07:00