72 lines
2.3 KiB
Verilog
72 lines
2.3 KiB
Verilog
//
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// TV80 8-Bit Microprocessor Core
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// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
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//
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// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and associated documentation files (the "Software"),
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// to deal in the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included
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// in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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module tv80_reg (/*AUTOARG*/
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// Outputs
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DOBH, DOAL, DOCL, DOBL, DOCH, DOAH,
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// Inputs
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AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
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);
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input [2:0] AddrC;
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output [7:0] DOBH;
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input [2:0] AddrA;
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input [2:0] AddrB;
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input [7:0] DIH;
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output [7:0] DOAL;
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output [7:0] DOCL;
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input [7:0] DIL;
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output [7:0] DOBL;
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output [7:0] DOCH;
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output [7:0] DOAH;
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input clk, CEN, WEH, WEL;
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reg [7:0] RegsH [0:7];
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reg [7:0] RegsL [0:7];
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always @(posedge clk)
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begin
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if (CEN)
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begin
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if (WEH) RegsH[AddrA] <= DIH;
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if (WEL) RegsL[AddrA] <= DIL;
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end
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end
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assign DOAH = RegsH[AddrA];
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assign DOAL = RegsL[AddrA];
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assign DOBH = RegsH[AddrB];
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assign DOBL = RegsL[AddrB];
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assign DOCH = RegsH[AddrC];
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assign DOCL = RegsL[AddrC];
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// break out ram bits for waveform debug
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wire [7:0] H = RegsH[2];
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wire [7:0] L = RegsL[2];
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// synopsys dc_script_begin
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// set_attribute current_design "revision" "$Id: tv80_reg.v,v 1.1 2004/05/16 17:39:57 ghutchis Exp $" -type string -quiet
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// synopsys dc_script_end
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endmodule
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