2760 lines
75 KiB
Verilog
2760 lines
75 KiB
Verilog
//
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// TV80 8-Bit Microprocessor Core
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// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
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//
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// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
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//
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// Permission is hereby granted, free of charge, to any person obtaining a
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// copy of this software and associated documentation files (the "Software"),
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// to deal in the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included
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// in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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module tv80_mcode (/*AUTOARG*/
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// Outputs
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MCycles, TStates, Prefix, Inc_PC, Inc_WZ, IncDec_16, Read_To_Reg,
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Read_To_Acc, Set_BusA_To, Set_BusB_To, ALU_Op, Save_ALU, PreserveC,
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Arith16, Set_Addr_To, IORQ, Jump, JumpE, JumpXY, Call, RstP, LDZ,
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LDW, LDSPHL, Special_LD, ExchangeDH, ExchangeRp, ExchangeAF,
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ExchangeRS, I_DJNZ, I_CPL, I_CCF, I_SCF, I_RETN, I_BT, I_BC, I_BTR,
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I_RLD, I_RRD, I_INRC, SetDI, SetEI, IMode, Halt, NoRead, Write,
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// Inputs
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IR, ISet, MCycle, F, NMICycle, IntCycle
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);
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parameter Mode = 0;
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parameter Flag_C = 0;
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parameter Flag_N = 1;
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parameter Flag_P = 2;
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parameter Flag_X = 3;
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parameter Flag_H = 4;
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parameter Flag_Y = 5;
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parameter Flag_Z = 6;
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parameter Flag_S = 7;
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input [7:0] IR;
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input [1:0] ISet ;
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input [2:0] MCycle ;
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input [7:0] F ;
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input NMICycle ;
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input IntCycle ;
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output [2:0] MCycles ;
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output [2:0] TStates ;
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output [1:0] Prefix ; // None,BC,ED,DD/FD
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output Inc_PC ;
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output Inc_WZ ;
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output [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc
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output Read_To_Reg ;
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output Read_To_Acc ;
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output [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
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output [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
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output [3:0] ALU_Op ;
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output Save_ALU ;
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output PreserveC ;
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output Arith16 ;
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output [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
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output IORQ ;
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output Jump ;
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output JumpE ;
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output JumpXY ;
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output Call ;
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output RstP ;
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output LDZ ;
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output LDW ;
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output LDSPHL ;
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output [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None
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output ExchangeDH ;
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output ExchangeRp ;
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output ExchangeAF ;
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output ExchangeRS ;
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output I_DJNZ ;
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output I_CPL ;
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output I_CCF ;
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output I_SCF ;
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output I_RETN ;
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output I_BT ;
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output I_BC ;
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output I_BTR ;
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output I_RLD ;
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output I_RRD ;
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output I_INRC ;
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output SetDI ;
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output SetEI ;
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output [1:0] IMode ;
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output Halt ;
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output NoRead ;
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output Write ;
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// regs
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reg [2:0] MCycles ;
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reg [2:0] TStates ;
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reg [1:0] Prefix ; // None,BC,ED,DD/FD
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reg Inc_PC ;
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reg Inc_WZ ;
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reg [3:0] IncDec_16 ; // BC,DE,HL,SP 0 is inc
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reg Read_To_Reg ;
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reg Read_To_Acc ;
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reg [3:0] Set_BusA_To ; // B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
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reg [3:0] Set_BusB_To ; // B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
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reg [3:0] ALU_Op ;
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reg Save_ALU ;
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reg PreserveC ;
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reg Arith16 ;
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reg [2:0] Set_Addr_To ; // aNone,aXY,aIOA,aSP,aBC,aDE,aZI
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reg IORQ ;
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reg Jump ;
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reg JumpE ;
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reg JumpXY ;
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reg Call ;
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reg RstP ;
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reg LDZ ;
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reg LDW ;
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reg LDSPHL ;
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reg [2:0] Special_LD ; // A,I;A,R;I,A;R,A;None
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reg ExchangeDH ;
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reg ExchangeRp ;
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reg ExchangeAF ;
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reg ExchangeRS ;
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reg I_DJNZ ;
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reg I_CPL ;
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reg I_CCF ;
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reg I_SCF ;
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reg I_RETN ;
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reg I_BT ;
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reg I_BC ;
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reg I_BTR ;
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reg I_RLD ;
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reg I_RRD ;
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reg I_INRC ;
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reg SetDI ;
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reg SetEI ;
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reg [1:0] IMode ;
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reg Halt ;
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reg NoRead ;
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reg Write ;
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parameter aNone = 3'b111;
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parameter aBC = 3'b000;
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parameter aDE = 3'b001;
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parameter aXY = 3'b010;
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parameter aIOA = 3'b100;
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parameter aSP = 3'b101;
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parameter aZI = 3'b110;
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// constant aNone : std_logic_vector[2:0] = 3'b000;
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// constant aXY : std_logic_vector[2:0] = 3'b001;
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// constant aIOA : std_logic_vector[2:0] = 3'b010;
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// constant aSP : std_logic_vector[2:0] = 3'b011;
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// constant aBC : std_logic_vector[2:0] = 3'b100;
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// constant aDE : std_logic_vector[2:0] = 3'b101;
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// constant aZI : std_logic_vector[2:0] = 3'b110;
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function is_cc_true;
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input [7:0] F;
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input [2:0] cc;
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begin
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if (Mode == 3 )
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begin
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case (cc)
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3'b000 : is_cc_true = F[7] == 1'b0; // NZ
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3'b001 : is_cc_true = F[7] == 1'b1; // Z
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3'b010 : is_cc_true = F[4] == 1'b0; // NC
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3'b011 : is_cc_true = F[4] == 1'b1; // C
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3'b100 : is_cc_true = 0;
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3'b101 : is_cc_true = 0;
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3'b110 : is_cc_true = 0;
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3'b111 : is_cc_true = 0;
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endcase
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end
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else
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begin
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case (cc)
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3'b000 : is_cc_true = F[6] == 1'b0; // NZ
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3'b001 : is_cc_true = F[6] == 1'b1; // Z
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3'b010 : is_cc_true = F[0] == 1'b0; // NC
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3'b011 : is_cc_true = F[0] == 1'b1; // C
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3'b100 : is_cc_true = F[2] == 1'b0; // PO
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3'b101 : is_cc_true = F[2] == 1'b1; // PE
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3'b110 : is_cc_true = F[7] == 1'b0; // P
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3'b111 : is_cc_true = F[7] == 1'b1; // M
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endcase
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end
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end
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endfunction // is_cc_true
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reg [2:0] DDD;
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reg [2:0] SSS;
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reg [1:0] DPAIR;
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reg [7:0] IRB;
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always @ (/*AUTOSENSE*/F or IR or ISet or IntCycle or MCycle
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or NMICycle)
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begin
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DDD = IR[5:3];
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SSS = IR[2:0];
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DPAIR = IR[5:4];
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IRB = IR;
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MCycles = 3'b001;
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if (MCycle == 3'b001 )
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begin
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TStates = 3'b100;
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end
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else
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begin
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TStates = 3'b011;
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end
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Prefix = 2'b00;
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Inc_PC = 1'b0;
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Inc_WZ = 1'b0;
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IncDec_16 = 4'b0000;
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Read_To_Acc = 1'b0;
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Read_To_Reg = 1'b0;
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Set_BusB_To = 4'b0000;
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Set_BusA_To = 4'b0000;
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ALU_Op = { 1'b0, IR[5:3] };
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Save_ALU = 1'b0;
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PreserveC = 1'b0;
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Arith16 = 1'b0;
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IORQ = 1'b0;
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Set_Addr_To = aNone;
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Jump = 1'b0;
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JumpE = 1'b0;
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JumpXY = 1'b0;
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Call = 1'b0;
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RstP = 1'b0;
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LDZ = 1'b0;
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LDW = 1'b0;
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LDSPHL = 1'b0;
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Special_LD = 3'b000;
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ExchangeDH = 1'b0;
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ExchangeRp = 1'b0;
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ExchangeAF = 1'b0;
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ExchangeRS = 1'b0;
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I_DJNZ = 1'b0;
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I_CPL = 1'b0;
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I_CCF = 1'b0;
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I_SCF = 1'b0;
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I_RETN = 1'b0;
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I_BT = 1'b0;
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I_BC = 1'b0;
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I_BTR = 1'b0;
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I_RLD = 1'b0;
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I_RRD = 1'b0;
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I_INRC = 1'b0;
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SetDI = 1'b0;
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SetEI = 1'b0;
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IMode = 2'b11;
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Halt = 1'b0;
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NoRead = 1'b0;
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Write = 1'b0;
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case (ISet)
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2'b00 :
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begin
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//----------------------------------------------------------------------------
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//
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// Unprefixed instructions
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//
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//----------------------------------------------------------------------------
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case (IRB)
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// 8 BIT LOAD GROUP
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8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,
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8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111,
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8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111,
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8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111,
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8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111,
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8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
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8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
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begin
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// LD r,r'
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Set_BusB_To[2:0] = SSS;
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ExchangeRp = 1'b1;
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Set_BusA_To[2:0] = DDD;
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Read_To_Reg = 1'b1;
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end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
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8'b00000110,8'b00001110,8'b00010110,8'b00011110,8'b00100110,8'b00101110,8'b00111110 :
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begin
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// LD r,n
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MCycles = 3'b010;
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case (MCycle)
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2 :
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begin
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Inc_PC = 1'b1;
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Set_BusA_To[2:0] = DDD;
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Read_To_Reg = 1'b1;
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end
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default :;
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endcase // case(MCycle)
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end // case: 8'b00000110,8'b00001110,8'b00010110,8'b00011110,8'b00100110,8'b00101110,8'b00111110
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8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110 :
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begin
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// LD r,(HL)
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MCycles = 3'b010;
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case (MCycle)
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1 :
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Set_Addr_To = aXY;
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2 :
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begin
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Set_BusA_To[2:0] = DDD;
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Read_To_Reg = 1'b1;
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end
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default :;
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endcase // case(MCycle)
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end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01111110
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8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111 :
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begin
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// LD (HL),r
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MCycles = 3'b010;
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case (MCycle)
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1 :
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begin
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Set_Addr_To = aXY;
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Set_BusB_To[2:0] = SSS;
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Set_BusB_To[3] = 1'b0;
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end
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2 :
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Write = 1'b1;
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default :;
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endcase // case(MCycle)
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end // case: 8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111
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8'b00110110 :
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begin
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// LD (HL),n
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MCycles = 3'b011;
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case (MCycle)
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2 :
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begin
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Inc_PC = 1'b1;
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Set_Addr_To = aXY;
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Set_BusB_To[2:0] = SSS;
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Set_BusB_To[3] = 1'b0;
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end
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3 :
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Write = 1'b1;
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default :;
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endcase // case(MCycle)
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end // case: 8'b00110110
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8'b00001010 :
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begin
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// LD A,(BC)
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MCycles = 3'b010;
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case (MCycle)
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1 :
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Set_Addr_To = aBC;
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2 :
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Read_To_Acc = 1'b1;
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default :;
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endcase // case(MCycle)
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end // case: 8'b00001010
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8'b00011010 :
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begin
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// LD A,(DE)
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MCycles = 3'b010;
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case (MCycle)
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1 :
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Set_Addr_To = aDE;
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2 :
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Read_To_Acc = 1'b1;
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default :;
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endcase // case(MCycle)
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end // case: 8'b00011010
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8'b00111010 :
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begin
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if (Mode == 3 )
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begin
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// LDD A,(HL)
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MCycles = 3'b010;
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case (MCycle)
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1 :
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Set_Addr_To = aXY;
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2 :
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begin
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Read_To_Acc = 1'b1;
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IncDec_16 = 4'b1110;
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end
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default :;
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endcase
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end
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else
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begin
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// LD A,(nn)
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MCycles = 3'b100;
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case (MCycle)
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2 :
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begin
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Inc_PC = 1'b1;
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LDZ = 1'b1;
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end
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3 :
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begin
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Set_Addr_To = aZI;
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Inc_PC = 1'b1;
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end
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4 :
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begin
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Read_To_Acc = 1'b1;
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end
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default :;
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endcase
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end // else: !if(Mode == 3 )
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end // case: 8'b00111010
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8'b00000010 :
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begin
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// LD (BC),A
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MCycles = 3'b010;
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case (MCycle)
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1 :
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begin
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Set_Addr_To = aBC;
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Set_BusB_To = 4'b0111;
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end
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2 :
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begin
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Write = 1'b1;
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end
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default :;
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endcase // case(MCycle)
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end // case: 8'b00000010
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8'b00010010 :
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begin
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// LD (DE),A
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MCycles = 3'b010;
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case (MCycle)
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1 :
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begin
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Set_Addr_To = aDE;
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Set_BusB_To = 4'b0111;
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end
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2 :
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Write = 1'b1;
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default :;
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endcase // case(MCycle)
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end // case: 8'b00010010
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8'b00110010 :
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begin
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if (Mode == 3 )
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begin
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// LDD (HL),A
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MCycles = 3'b010;
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case (MCycle)
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1 :
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begin
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Set_Addr_To = aXY;
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Set_BusB_To = 4'b0111;
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end
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2 :
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begin
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Write = 1'b1;
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IncDec_16 = 4'b1110;
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end
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default :;
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endcase // case(MCycle)
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end
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else
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begin
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// LD (nn),A
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MCycles = 3'b100;
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case (MCycle)
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2 :
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begin
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|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
3 :
|
|
begin
|
|
Set_Addr_To = aZI;
|
|
Inc_PC = 1'b1;
|
|
Set_BusB_To = 4'b0111;
|
|
end
|
|
4 :
|
|
begin
|
|
Write = 1'b1;
|
|
end
|
|
default :;
|
|
endcase
|
|
end // else: !if(Mode == 3 )
|
|
end // case: 8'b00110010
|
|
|
|
|
|
// 16 BIT LOAD GROUP
|
|
8'b00000001,8'b00010001,8'b00100001,8'b00110001 :
|
|
begin
|
|
// LD dd,nn
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
Read_To_Reg = 1'b1;
|
|
if (DPAIR == 2'b11 )
|
|
begin
|
|
Set_BusA_To[3:0] = 4'b1000;
|
|
end
|
|
else
|
|
begin
|
|
Set_BusA_To[2:1] = DPAIR;
|
|
Set_BusA_To[0] = 1'b1;
|
|
end
|
|
end // case: 2
|
|
|
|
3 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
Read_To_Reg = 1'b1;
|
|
if (DPAIR == 2'b11 )
|
|
begin
|
|
Set_BusA_To[3:0] = 4'b1001;
|
|
end
|
|
else
|
|
begin
|
|
Set_BusA_To[2:1] = DPAIR;
|
|
Set_BusA_To[0] = 1'b0;
|
|
end
|
|
end // case: 3
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b00000001,8'b00010001,8'b00100001,8'b00110001
|
|
|
|
8'b00101010 :
|
|
begin
|
|
if (Mode == 3 )
|
|
begin
|
|
// LDI A,(HL)
|
|
MCycles = 3'b010;
|
|
case (MCycle)
|
|
1 :
|
|
Set_Addr_To = aXY;
|
|
2 :
|
|
begin
|
|
Read_To_Acc = 1'b1;
|
|
IncDec_16 = 4'b0110;
|
|
end
|
|
|
|
default :;
|
|
endcase
|
|
end
|
|
else
|
|
begin
|
|
// LD HL,(nn)
|
|
MCycles = 3'b101;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
3 :
|
|
begin
|
|
Set_Addr_To = aZI;
|
|
Inc_PC = 1'b1;
|
|
LDW = 1'b1;
|
|
end
|
|
4 :
|
|
begin
|
|
Set_BusA_To[2:0] = 3'b101; // L
|
|
Read_To_Reg = 1'b1;
|
|
Inc_WZ = 1'b1;
|
|
Set_Addr_To = aZI;
|
|
end
|
|
5 :
|
|
begin
|
|
Set_BusA_To[2:0] = 3'b100; // H
|
|
Read_To_Reg = 1'b1;
|
|
end
|
|
default :;
|
|
endcase
|
|
end // else: !if(Mode == 3 )
|
|
end // case: 8'b00101010
|
|
|
|
8'b00100010 :
|
|
begin
|
|
if (Mode == 3 )
|
|
begin
|
|
// LDI (HL),A
|
|
MCycles = 3'b010;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
Set_Addr_To = aXY;
|
|
Set_BusB_To = 4'b0111;
|
|
end
|
|
2 :
|
|
begin
|
|
Write = 1'b1;
|
|
IncDec_16 = 4'b0110;
|
|
end
|
|
default :;
|
|
endcase
|
|
end
|
|
else
|
|
begin
|
|
// LD (nn),HL
|
|
MCycles = 3'b101;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Set_Addr_To = aZI;
|
|
Inc_PC = 1'b1;
|
|
LDW = 1'b1;
|
|
Set_BusB_To = 4'b0101; // L
|
|
end
|
|
|
|
4 :
|
|
begin
|
|
Inc_WZ = 1'b1;
|
|
Set_Addr_To = aZI;
|
|
Write = 1'b1;
|
|
Set_BusB_To = 4'b0100; // H
|
|
end
|
|
5 :
|
|
Write = 1'b1;
|
|
default :;
|
|
endcase
|
|
end // else: !if(Mode == 3 )
|
|
end // case: 8'b00100010
|
|
|
|
8'b11111001 :
|
|
begin
|
|
// LD SP,HL
|
|
TStates = 3'b110;
|
|
LDSPHL = 1'b1;
|
|
end
|
|
|
|
8'b11000101,8'b11010101,8'b11100101,8'b11110101 :
|
|
begin
|
|
// PUSH qq
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
TStates = 3'b101;
|
|
IncDec_16 = 4'b1111;
|
|
Set_Addr_To = aSP;
|
|
if (DPAIR == 2'b11 )
|
|
begin
|
|
Set_BusB_To = 4'b0111;
|
|
end
|
|
else
|
|
begin
|
|
Set_BusB_To[2:1] = DPAIR;
|
|
Set_BusB_To[0] = 1'b0;
|
|
Set_BusB_To[3] = 1'b0;
|
|
end
|
|
end // case: 1
|
|
|
|
2 :
|
|
begin
|
|
IncDec_16 = 4'b1111;
|
|
Set_Addr_To = aSP;
|
|
if (DPAIR == 2'b11 )
|
|
begin
|
|
Set_BusB_To = 4'b1011;
|
|
end
|
|
else
|
|
begin
|
|
Set_BusB_To[2:1] = DPAIR;
|
|
Set_BusB_To[0] = 1'b1;
|
|
Set_BusB_To[3] = 1'b0;
|
|
end
|
|
Write = 1'b1;
|
|
end // case: 2
|
|
|
|
3 :
|
|
Write = 1'b1;
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b11000101,8'b11010101,8'b11100101,8'b11110101
|
|
|
|
8'b11000001,8'b11010001,8'b11100001,8'b11110001 :
|
|
begin
|
|
// POP qq
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 :
|
|
Set_Addr_To = aSP;
|
|
2 :
|
|
begin
|
|
IncDec_16 = 4'b0111;
|
|
Set_Addr_To = aSP;
|
|
Read_To_Reg = 1'b1;
|
|
if (DPAIR == 2'b11 )
|
|
begin
|
|
Set_BusA_To[3:0] = 4'b1011;
|
|
end
|
|
else
|
|
begin
|
|
Set_BusA_To[2:1] = DPAIR;
|
|
Set_BusA_To[0] = 1'b1;
|
|
end
|
|
end // case: 2
|
|
|
|
3 :
|
|
begin
|
|
IncDec_16 = 4'b0111;
|
|
Read_To_Reg = 1'b1;
|
|
if (DPAIR == 2'b11 )
|
|
begin
|
|
Set_BusA_To[3:0] = 4'b0111;
|
|
end
|
|
else
|
|
begin
|
|
Set_BusA_To[2:1] = DPAIR;
|
|
Set_BusA_To[0] = 1'b0;
|
|
end
|
|
end // case: 3
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b11000001,8'b11010001,8'b11100001,8'b11110001
|
|
|
|
|
|
// EXCHANGE, BLOCK TRANSFER AND SEARCH GROUP
|
|
8'b11101011 :
|
|
begin
|
|
if (Mode != 3 )
|
|
begin
|
|
// EX DE,HL
|
|
ExchangeDH = 1'b1;
|
|
end
|
|
end
|
|
|
|
8'b00001000 :
|
|
begin
|
|
if (Mode == 3 )
|
|
begin
|
|
// LD (nn),SP
|
|
MCycles = 3'b101;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Set_Addr_To = aZI;
|
|
Inc_PC = 1'b1;
|
|
LDW = 1'b1;
|
|
Set_BusB_To = 4'b1000;
|
|
end
|
|
|
|
4 :
|
|
begin
|
|
Inc_WZ = 1'b1;
|
|
Set_Addr_To = aZI;
|
|
Write = 1'b1;
|
|
Set_BusB_To = 4'b1001;
|
|
end
|
|
|
|
5 :
|
|
Write = 1'b1;
|
|
default :;
|
|
endcase
|
|
end
|
|
else if (Mode < 2 )
|
|
begin
|
|
// EX AF,AF'
|
|
ExchangeAF = 1'b1;
|
|
end
|
|
end // case: 8'b00001000
|
|
|
|
8'b11011001 :
|
|
begin
|
|
if (Mode == 3 )
|
|
begin
|
|
// RETI
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 :
|
|
Set_Addr_To = aSP;
|
|
2 :
|
|
begin
|
|
IncDec_16 = 4'b0111;
|
|
Set_Addr_To = aSP;
|
|
LDZ = 1'b1;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Jump = 1'b1;
|
|
IncDec_16 = 4'b0111;
|
|
I_RETN = 1'b1;
|
|
SetEI = 1'b1;
|
|
end
|
|
default :;
|
|
endcase
|
|
end
|
|
else if (Mode < 2 )
|
|
begin
|
|
// EXX
|
|
ExchangeRS = 1'b1;
|
|
end
|
|
end // case: 8'b11011001
|
|
|
|
8'b11100011 :
|
|
begin
|
|
if (Mode != 3 )
|
|
begin
|
|
// EX (SP),HL
|
|
MCycles = 3'b101;
|
|
case (MCycle)
|
|
1 :
|
|
Set_Addr_To = aSP;
|
|
2 :
|
|
begin
|
|
Read_To_Reg = 1'b1;
|
|
Set_BusA_To = 4'b0101;
|
|
Set_BusB_To = 4'b0101;
|
|
Set_Addr_To = aSP;
|
|
end
|
|
3 :
|
|
begin
|
|
IncDec_16 = 4'b0111;
|
|
Set_Addr_To = aSP;
|
|
TStates = 3'b100;
|
|
Write = 1'b1;
|
|
end
|
|
4 :
|
|
begin
|
|
Read_To_Reg = 1'b1;
|
|
Set_BusA_To = 4'b0100;
|
|
Set_BusB_To = 4'b0100;
|
|
Set_Addr_To = aSP;
|
|
end
|
|
5 :
|
|
begin
|
|
IncDec_16 = 4'b1111;
|
|
TStates = 3'b101;
|
|
Write = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase
|
|
end // if (Mode != 3 )
|
|
end // case: 8'b11100011
|
|
|
|
|
|
// 8 BIT ARITHMETIC AND LOGICAL GROUP
|
|
8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,
|
|
8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111,
|
|
8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111,
|
|
8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111,
|
|
8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111,
|
|
8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
|
|
8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
|
|
8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
|
|
begin
|
|
// ADD A,r
|
|
// ADC A,r
|
|
// SUB A,r
|
|
// SBC A,r
|
|
// AND A,r
|
|
// OR A,r
|
|
// XOR A,r
|
|
// CP A,r
|
|
Set_BusB_To[2:0] = SSS;
|
|
Set_BusA_To[2:0] = 3'b111;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
|
|
|
|
8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 :
|
|
begin
|
|
// ADD A,(HL)
|
|
// ADC A,(HL)
|
|
// SUB A,(HL)
|
|
// SBC A,(HL)
|
|
// AND A,(HL)
|
|
// OR A,(HL)
|
|
// XOR A,(HL)
|
|
// CP A,(HL)
|
|
MCycles = 3'b010;
|
|
case (MCycle)
|
|
1 :
|
|
Set_Addr_To = aXY;
|
|
2 :
|
|
begin
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
Set_BusB_To[2:0] = SSS;
|
|
Set_BusA_To[2:0] = 3'b111;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
|
|
|
|
8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 :
|
|
begin
|
|
// ADD A,n
|
|
// ADC A,n
|
|
// SUB A,n
|
|
// SBC A,n
|
|
// AND A,n
|
|
// OR A,n
|
|
// XOR A,n
|
|
// CP A,n
|
|
MCycles = 3'b010;
|
|
if (MCycle == 3'b010 )
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
Set_BusB_To[2:0] = SSS;
|
|
Set_BusA_To[2:0] = 3'b111;
|
|
end
|
|
end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
|
|
|
|
8'b00000100,8'b00001100,8'b00010100,8'b00011100,8'b00100100,8'b00101100,8'b00111100 :
|
|
begin
|
|
// INC r
|
|
Set_BusB_To = 4'b1010;
|
|
Set_BusA_To[2:0] = DDD;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
PreserveC = 1'b1;
|
|
ALU_Op = 4'b0000;
|
|
end
|
|
|
|
8'b00110100 :
|
|
begin
|
|
// INC (HL)
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 :
|
|
Set_Addr_To = aXY;
|
|
2 :
|
|
begin
|
|
TStates = 3'b100;
|
|
Set_Addr_To = aXY;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
PreserveC = 1'b1;
|
|
ALU_Op = 4'b0000;
|
|
Set_BusB_To = 4'b1010;
|
|
Set_BusA_To[2:0] = DDD;
|
|
end // case: 2
|
|
|
|
3 :
|
|
Write = 1'b1;
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b00110100
|
|
|
|
8'b00000101,8'b00001101,8'b00010101,8'b00011101,8'b00100101,8'b00101101,8'b00111101 :
|
|
begin
|
|
// DEC r
|
|
Set_BusB_To = 4'b1010;
|
|
Set_BusA_To[2:0] = DDD;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
PreserveC = 1'b1;
|
|
ALU_Op = 4'b0010;
|
|
end
|
|
|
|
8'b00110101 :
|
|
begin
|
|
// DEC (HL)
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 :
|
|
Set_Addr_To = aXY;
|
|
2 :
|
|
begin
|
|
TStates = 3'b100;
|
|
Set_Addr_To = aXY;
|
|
ALU_Op = 4'b0010;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
PreserveC = 1'b1;
|
|
Set_BusB_To = 4'b1010;
|
|
Set_BusA_To[2:0] = DDD;
|
|
end // case: 2
|
|
|
|
3 :
|
|
Write = 1'b1;
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b00110101
|
|
|
|
// GENERAL PURPOSE ARITHMETIC AND CPU CONTROL GROUPS
|
|
8'b00100111 :
|
|
begin
|
|
// DAA
|
|
Set_BusA_To[2:0] = 3'b111;
|
|
Read_To_Reg = 1'b1;
|
|
ALU_Op = 4'b1100;
|
|
Save_ALU = 1'b1;
|
|
end
|
|
|
|
8'b00101111 :
|
|
// CPL
|
|
I_CPL = 1'b1;
|
|
|
|
8'b00111111 :
|
|
// CCF
|
|
I_CCF = 1'b1;
|
|
|
|
8'b00110111 :
|
|
// SCF
|
|
I_SCF = 1'b1;
|
|
|
|
8'b00000000 :
|
|
begin
|
|
if (NMICycle == 1'b1 )
|
|
begin
|
|
// NMI
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
TStates = 3'b101;
|
|
IncDec_16 = 4'b1111;
|
|
Set_Addr_To = aSP;
|
|
Set_BusB_To = 4'b1101;
|
|
end
|
|
|
|
2 :
|
|
begin
|
|
TStates = 3'b100;
|
|
Write = 1'b1;
|
|
IncDec_16 = 4'b1111;
|
|
Set_Addr_To = aSP;
|
|
Set_BusB_To = 4'b1100;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
TStates = 3'b100;
|
|
Write = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
|
|
end
|
|
else if (IntCycle == 1'b1 )
|
|
begin
|
|
// INT (IM 2)
|
|
MCycles = 3'b101;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
LDZ = 1'b1;
|
|
TStates = 3'b101;
|
|
IncDec_16 = 4'b1111;
|
|
Set_Addr_To = aSP;
|
|
Set_BusB_To = 4'b1101;
|
|
end
|
|
|
|
2 :
|
|
begin
|
|
TStates = 3'b100;
|
|
Write = 1'b1;
|
|
IncDec_16 = 4'b1111;
|
|
Set_Addr_To = aSP;
|
|
Set_BusB_To = 4'b1100;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
TStates = 3'b100;
|
|
Write = 1'b1;
|
|
end
|
|
|
|
4 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
|
|
5 :
|
|
Jump = 1'b1;
|
|
default :;
|
|
endcase
|
|
end
|
|
end // case: 8'b00000000
|
|
|
|
8'b01110110 :
|
|
// HALT
|
|
Halt = 1'b1;
|
|
|
|
8'b11110011 :
|
|
// DI
|
|
SetDI = 1'b1;
|
|
|
|
8'b11111011 :
|
|
// EI
|
|
SetEI = 1'b1;
|
|
|
|
// 16 BIT ARITHMETIC GROUP
|
|
8'b00001001,8'b00011001,8'b00101001,8'b00111001 :
|
|
begin
|
|
// ADD HL,ss
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
ALU_Op = 4'b0000;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
Set_BusA_To[2:0] = 3'b101;
|
|
case (IR[5:4])
|
|
0,1,2 :
|
|
begin
|
|
Set_BusB_To[2:1] = IR[5:4];
|
|
Set_BusB_To[0] = 1'b1;
|
|
end
|
|
|
|
default :
|
|
Set_BusB_To = 4'b1000;
|
|
endcase // case(IR[5:4])
|
|
|
|
TStates = 3'b100;
|
|
Arith16 = 1'b1;
|
|
end // case: 2
|
|
|
|
3 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
ALU_Op = 4'b0001;
|
|
Set_BusA_To[2:0] = 3'b100;
|
|
case (IR[5:4])
|
|
0,1,2 :
|
|
Set_BusB_To[2:1] = IR[5:4];
|
|
default :
|
|
Set_BusB_To = 4'b1001;
|
|
endcase
|
|
Arith16 = 1'b1;
|
|
end // case: 3
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b00001001,8'b00011001,8'b00101001,8'b00111001
|
|
|
|
8'b00000011,8'b00010011,8'b00100011,8'b00110011 :
|
|
begin
|
|
// INC ss
|
|
TStates = 3'b110;
|
|
IncDec_16[3:2] = 2'b01;
|
|
IncDec_16[1:0] = DPAIR;
|
|
end
|
|
|
|
8'b00001011,8'b00011011,8'b00101011,8'b00111011 :
|
|
begin
|
|
// DEC ss
|
|
TStates = 3'b110;
|
|
IncDec_16[3:2] = 2'b11;
|
|
IncDec_16[1:0] = DPAIR;
|
|
end
|
|
|
|
// ROTATE AND SHIFT GROUP
|
|
8'b00000111,
|
|
// RLCA
|
|
8'b00010111,
|
|
// RLA
|
|
8'b00001111,
|
|
// RRCA
|
|
8'b00011111 :
|
|
// RRA
|
|
begin
|
|
Set_BusA_To[2:0] = 3'b111;
|
|
ALU_Op = 4'b1000;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
end // case: 8'b00000111,...
|
|
|
|
|
|
// JUMP GROUP
|
|
8'b11000011 :
|
|
begin
|
|
// JP nn
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
Jump = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b11000011
|
|
|
|
8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010 :
|
|
begin
|
|
if (IR[5] == 1'b1 && Mode == 3 )
|
|
begin
|
|
case (IRB[4:3])
|
|
2'b00 :
|
|
begin
|
|
// LD ($FF00+C),A
|
|
MCycles = 3'b010;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
Set_Addr_To = aBC;
|
|
Set_BusB_To = 4'b0111;
|
|
end
|
|
2 :
|
|
begin
|
|
Write = 1'b1;
|
|
IORQ = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 2'b00
|
|
|
|
2'b01 :
|
|
begin
|
|
// LD (nn),A
|
|
MCycles = 3'b100;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Set_Addr_To = aZI;
|
|
Inc_PC = 1'b1;
|
|
Set_BusB_To = 4'b0111;
|
|
end
|
|
|
|
4 :
|
|
Write = 1'b1;
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: default :...
|
|
|
|
2'b10 :
|
|
begin
|
|
// LD A,($FF00+C)
|
|
MCycles = 3'b010;
|
|
case (MCycle)
|
|
1 :
|
|
Set_Addr_To = aBC;
|
|
2 :
|
|
begin
|
|
Read_To_Acc = 1'b1;
|
|
IORQ = 1'b1;
|
|
end
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 2'b10
|
|
|
|
2'b11 :
|
|
begin
|
|
// LD A,(nn)
|
|
MCycles = 3'b100;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
3 :
|
|
begin
|
|
Set_Addr_To = aZI;
|
|
Inc_PC = 1'b1;
|
|
end
|
|
4 :
|
|
Read_To_Acc = 1'b1;
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end
|
|
endcase
|
|
end
|
|
else
|
|
begin
|
|
// JP cc,nn
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
3 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
if (is_cc_true(F, IR[5:3]) )
|
|
begin
|
|
Jump = 1'b1;
|
|
end
|
|
end
|
|
|
|
default :;
|
|
endcase
|
|
end // else: !if(DPAIR == 2'b11 )
|
|
end // case: 8'b11000010,8'b11001010,8'b11010010,8'b11011010,8'b11100010,8'b11101010,8'b11110010,8'b11111010
|
|
|
|
8'b00011000 :
|
|
begin
|
|
if (Mode != 2 )
|
|
begin
|
|
// JR e
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
Inc_PC = 1'b1;
|
|
3 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
JumpE = 1'b1;
|
|
TStates = 3'b101;
|
|
end
|
|
default :;
|
|
endcase
|
|
end // if (Mode != 2 )
|
|
end // case: 8'b00011000
|
|
|
|
8'b00111000 :
|
|
begin
|
|
if (Mode != 2 )
|
|
begin
|
|
// JR C,e
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
if (F[Flag_C] == 1'b0 )
|
|
begin
|
|
MCycles = 3'b010;
|
|
end
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
JumpE = 1'b1;
|
|
TStates = 3'b101;
|
|
end
|
|
default :;
|
|
endcase
|
|
end // if (Mode != 2 )
|
|
end // case: 8'b00111000
|
|
|
|
8'b00110000 :
|
|
begin
|
|
if (Mode != 2 )
|
|
begin
|
|
// JR NC,e
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
if (F[Flag_C] == 1'b1 )
|
|
begin
|
|
MCycles = 3'b010;
|
|
end
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
JumpE = 1'b1;
|
|
TStates = 3'b101;
|
|
end
|
|
default :;
|
|
endcase
|
|
end // if (Mode != 2 )
|
|
end // case: 8'b00110000
|
|
|
|
8'b00101000 :
|
|
begin
|
|
if (Mode != 2 )
|
|
begin
|
|
// JR Z,e
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
if (F[Flag_Z] == 1'b0 )
|
|
begin
|
|
MCycles = 3'b010;
|
|
end
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
JumpE = 1'b1;
|
|
TStates = 3'b101;
|
|
end
|
|
|
|
default :;
|
|
endcase
|
|
end // if (Mode != 2 )
|
|
end // case: 8'b00101000
|
|
|
|
8'b00100000 :
|
|
begin
|
|
if (Mode != 2 )
|
|
begin
|
|
// JR NZ,e
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
if (F[Flag_Z] == 1'b1 )
|
|
begin
|
|
MCycles = 3'b010;
|
|
end
|
|
end
|
|
3 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
JumpE = 1'b1;
|
|
TStates = 3'b101;
|
|
end
|
|
default :;
|
|
endcase
|
|
end // if (Mode != 2 )
|
|
end // case: 8'b00100000
|
|
|
|
8'b11101001 :
|
|
// JP (HL)
|
|
JumpXY = 1'b1;
|
|
|
|
8'b00010000 :
|
|
begin
|
|
if (Mode == 3 )
|
|
begin
|
|
I_DJNZ = 1'b1;
|
|
end
|
|
else if (Mode < 2 )
|
|
begin
|
|
// DJNZ,e
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
TStates = 3'b101;
|
|
I_DJNZ = 1'b1;
|
|
Set_BusB_To = 4'b1010;
|
|
Set_BusA_To[2:0] = 3'b000;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
ALU_Op = 4'b0010;
|
|
end
|
|
2 :
|
|
begin
|
|
I_DJNZ = 1'b1;
|
|
Inc_PC = 1'b1;
|
|
end
|
|
3 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
JumpE = 1'b1;
|
|
TStates = 3'b101;
|
|
end
|
|
default :;
|
|
endcase
|
|
end // if (Mode < 2 )
|
|
end // case: 8'b00010000
|
|
|
|
|
|
// CALL AND RETURN GROUP
|
|
8'b11001101 :
|
|
begin
|
|
// CALL nn
|
|
MCycles = 3'b101;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
3 :
|
|
begin
|
|
IncDec_16 = 4'b1111;
|
|
Inc_PC = 1'b1;
|
|
TStates = 3'b100;
|
|
Set_Addr_To = aSP;
|
|
LDW = 1'b1;
|
|
Set_BusB_To = 4'b1101;
|
|
end
|
|
4 :
|
|
begin
|
|
Write = 1'b1;
|
|
IncDec_16 = 4'b1111;
|
|
Set_Addr_To = aSP;
|
|
Set_BusB_To = 4'b1100;
|
|
end
|
|
5 :
|
|
begin
|
|
Write = 1'b1;
|
|
Call = 1'b1;
|
|
end
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b11001101
|
|
|
|
8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100 :
|
|
begin
|
|
if (IR[5] == 1'b0 || Mode != 3 )
|
|
begin
|
|
// CALL cc,nn
|
|
MCycles = 3'b101;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
3 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDW = 1'b1;
|
|
if (is_cc_true(F, IR[5:3]) )
|
|
begin
|
|
IncDec_16 = 4'b1111;
|
|
Set_Addr_To = aSP;
|
|
TStates = 3'b100;
|
|
Set_BusB_To = 4'b1101;
|
|
end
|
|
else
|
|
begin
|
|
MCycles = 3'b011;
|
|
end // else: !if(is_cc_true(F, IR[5:3]) )
|
|
end // case: 3
|
|
|
|
4 :
|
|
begin
|
|
Write = 1'b1;
|
|
IncDec_16 = 4'b1111;
|
|
Set_Addr_To = aSP;
|
|
Set_BusB_To = 4'b1100;
|
|
end
|
|
|
|
5 :
|
|
begin
|
|
Write = 1'b1;
|
|
Call = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase
|
|
end // if (IR[5] == 1'b0 || Mode != 3 )
|
|
end // case: 8'b11000100,8'b11001100,8'b11010100,8'b11011100,8'b11100100,8'b11101100,8'b11110100,8'b11111100
|
|
|
|
8'b11001001 :
|
|
begin
|
|
// RET
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
TStates = 3'b101;
|
|
Set_Addr_To = aSP;
|
|
end
|
|
|
|
2 :
|
|
begin
|
|
IncDec_16 = 4'b0111;
|
|
Set_Addr_To = aSP;
|
|
LDZ = 1'b1;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Jump = 1'b1;
|
|
IncDec_16 = 4'b0111;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b11001001
|
|
|
|
8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000 :
|
|
begin
|
|
if (IR[5] == 1'b1 && Mode == 3 )
|
|
begin
|
|
case (IRB[4:3])
|
|
2'b00 :
|
|
begin
|
|
// LD ($FF00+nn),A
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
Set_Addr_To = aIOA;
|
|
Set_BusB_To = 4'b0111;
|
|
end
|
|
|
|
3 :
|
|
Write = 1'b1;
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 2'b00
|
|
|
|
2'b01 :
|
|
begin
|
|
// ADD SP,n
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
ALU_Op = 4'b0000;
|
|
Inc_PC = 1'b1;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
Set_BusA_To = 4'b1000;
|
|
Set_BusB_To = 4'b0110;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
ALU_Op = 4'b0001;
|
|
Set_BusA_To = 4'b1001;
|
|
Set_BusB_To = 4'b1110; // Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 2'b01
|
|
|
|
2'b10 :
|
|
begin
|
|
// LD A,($FF00+nn)
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
Set_Addr_To = aIOA;
|
|
end
|
|
|
|
3 :
|
|
Read_To_Acc = 1'b1;
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 2'b10
|
|
|
|
2'b11 :
|
|
begin
|
|
// LD HL,SP+n -- Not correct !!!!!!!!!!!!!!!!!!!
|
|
MCycles = 3'b101;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Set_Addr_To = aZI;
|
|
Inc_PC = 1'b1;
|
|
LDW = 1'b1;
|
|
end
|
|
|
|
4 :
|
|
begin
|
|
Set_BusA_To[2:0] = 3'b101; // L
|
|
Read_To_Reg = 1'b1;
|
|
Inc_WZ = 1'b1;
|
|
Set_Addr_To = aZI;
|
|
end
|
|
|
|
5 :
|
|
begin
|
|
Set_BusA_To[2:0] = 3'b100; // H
|
|
Read_To_Reg = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 2'b11
|
|
|
|
endcase // case(IRB[4:3])
|
|
|
|
end
|
|
else
|
|
begin
|
|
// RET cc
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
if (is_cc_true(F, IR[5:3]) )
|
|
begin
|
|
Set_Addr_To = aSP;
|
|
end
|
|
else
|
|
begin
|
|
MCycles = 3'b001;
|
|
end
|
|
TStates = 3'b101;
|
|
end // case: 1
|
|
|
|
2 :
|
|
begin
|
|
IncDec_16 = 4'b0111;
|
|
Set_Addr_To = aSP;
|
|
LDZ = 1'b1;
|
|
end
|
|
3 :
|
|
begin
|
|
Jump = 1'b1;
|
|
IncDec_16 = 4'b0111;
|
|
end
|
|
default :;
|
|
endcase
|
|
end // else: !if(IR[5] == 1'b1 && Mode == 3 )
|
|
end // case: 8'b11000000,8'b11001000,8'b11010000,8'b11011000,8'b11100000,8'b11101000,8'b11110000,8'b11111000
|
|
|
|
8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111 :
|
|
begin
|
|
// RST p
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
TStates = 3'b101;
|
|
IncDec_16 = 4'b1111;
|
|
Set_Addr_To = aSP;
|
|
Set_BusB_To = 4'b1101;
|
|
end
|
|
|
|
2 :
|
|
begin
|
|
Write = 1'b1;
|
|
IncDec_16 = 4'b1111;
|
|
Set_Addr_To = aSP;
|
|
Set_BusB_To = 4'b1100;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Write = 1'b1;
|
|
RstP = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b11000111,8'b11001111,8'b11010111,8'b11011111,8'b11100111,8'b11101111,8'b11110111,8'b11111111
|
|
|
|
// INPUT AND OUTPUT GROUP
|
|
8'b11011011 :
|
|
begin
|
|
if (Mode != 3 )
|
|
begin
|
|
// IN A,(n)
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
Set_Addr_To = aIOA;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Read_To_Acc = 1'b1;
|
|
IORQ = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase
|
|
end // if (Mode != 3 )
|
|
end // case: 8'b11011011
|
|
|
|
8'b11010011 :
|
|
begin
|
|
if (Mode != 3 )
|
|
begin
|
|
// OUT (n),A
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
Set_Addr_To = aIOA;
|
|
Set_BusB_To = 4'b0111;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Write = 1'b1;
|
|
IORQ = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase
|
|
end // if (Mode != 3 )
|
|
end // case: 8'b11010011
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
//----------------------------------------------------------------------------
|
|
// MULTIBYTE INSTRUCTIONS
|
|
//----------------------------------------------------------------------------
|
|
//----------------------------------------------------------------------------
|
|
|
|
8'b11001011 :
|
|
begin
|
|
if (Mode != 2 )
|
|
begin
|
|
Prefix = 2'b01;
|
|
end
|
|
end
|
|
|
|
8'b11101101 :
|
|
begin
|
|
if (Mode < 2 )
|
|
begin
|
|
Prefix = 2'b10;
|
|
end
|
|
end
|
|
|
|
8'b11011101,8'b11111101 :
|
|
begin
|
|
if (Mode < 2 )
|
|
begin
|
|
Prefix = 2'b11;
|
|
end
|
|
end
|
|
|
|
endcase // case(IRB)
|
|
end // case: 2'b00
|
|
|
|
|
|
2'b01 :
|
|
begin
|
|
|
|
|
|
//----------------------------------------------------------------------------
|
|
//
|
|
// CB prefixed instructions
|
|
//
|
|
//----------------------------------------------------------------------------
|
|
|
|
Set_BusA_To[2:0] = IR[2:0];
|
|
Set_BusB_To[2:0] = IR[2:0];
|
|
|
|
case (IRB)
|
|
8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,
|
|
8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010111,
|
|
8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001111,
|
|
8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011111,
|
|
8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100111,
|
|
8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101111,
|
|
8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110111,
|
|
8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111111 :
|
|
begin
|
|
// RLC r
|
|
// RL r
|
|
// RRC r
|
|
// RR r
|
|
// SLA r
|
|
// SRA r
|
|
// SRL r
|
|
// SLL r (Undocumented) / SWAP r
|
|
if (MCycle == 3'b001 ) begin
|
|
ALU_Op = 4'b1000;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
end
|
|
end // case: 8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000111,...
|
|
|
|
8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110 :
|
|
begin
|
|
// RLC (HL)
|
|
// RL (HL)
|
|
// RRC (HL)
|
|
// RR (HL)
|
|
// SRA (HL)
|
|
// SRL (HL)
|
|
// SLA (HL)
|
|
// SLL (HL) (Undocumented) / SWAP (HL)
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 , 7 :
|
|
Set_Addr_To = aXY;
|
|
2 :
|
|
begin
|
|
ALU_Op = 4'b1000;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
Set_Addr_To = aXY;
|
|
TStates = 3'b100;
|
|
end
|
|
|
|
3 :
|
|
Write = 1'b1;
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b00000110,8'b00010110,8'b00001110,8'b00011110,8'b00101110,8'b00111110,8'b00100110,8'b00110110
|
|
|
|
8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,
|
|
8'b01001000,8'b01001001,8'b01001010,8'b01001011,8'b01001100,8'b01001101,8'b01001111,
|
|
8'b01010000,8'b01010001,8'b01010010,8'b01010011,8'b01010100,8'b01010101,8'b01010111,
|
|
8'b01011000,8'b01011001,8'b01011010,8'b01011011,8'b01011100,8'b01011101,8'b01011111,
|
|
8'b01100000,8'b01100001,8'b01100010,8'b01100011,8'b01100100,8'b01100101,8'b01100111,
|
|
8'b01101000,8'b01101001,8'b01101010,8'b01101011,8'b01101100,8'b01101101,8'b01101111,
|
|
8'b01110000,8'b01110001,8'b01110010,8'b01110011,8'b01110100,8'b01110101,8'b01110111,
|
|
8'b01111000,8'b01111001,8'b01111010,8'b01111011,8'b01111100,8'b01111101,8'b01111111 :
|
|
begin
|
|
// BIT b,r
|
|
if (MCycle == 3'b001 )
|
|
begin
|
|
Set_BusB_To[2:0] = IR[2:0];
|
|
ALU_Op = 4'b1001;
|
|
end
|
|
end // case: 8'b01000000,8'b01000001,8'b01000010,8'b01000011,8'b01000100,8'b01000101,8'b01000111,...
|
|
|
|
8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110 :
|
|
begin
|
|
// BIT b,(HL)
|
|
MCycles = 3'b010;
|
|
case (MCycle)
|
|
1 , 7 :
|
|
Set_Addr_To = aXY;
|
|
2 :
|
|
begin
|
|
ALU_Op = 4'b1001;
|
|
TStates = 3'b100;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b01000110,8'b01001110,8'b01010110,8'b01011110,8'b01100110,8'b01101110,8'b01110110,8'b01111110
|
|
|
|
8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,
|
|
8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001111,
|
|
8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010111,
|
|
8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011111,
|
|
8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100111,
|
|
8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101111,
|
|
8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110111,
|
|
8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111111 :
|
|
begin
|
|
// SET b,r
|
|
if (MCycle == 3'b001 )
|
|
begin
|
|
ALU_Op = 4'b1010;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
end
|
|
end // case: 8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000111,...
|
|
|
|
8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110 :
|
|
begin
|
|
// SET b,(HL)
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 , 7 :
|
|
Set_Addr_To = aXY;
|
|
2 :
|
|
begin
|
|
ALU_Op = 4'b1010;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
Set_Addr_To = aXY;
|
|
TStates = 3'b100;
|
|
end
|
|
3 :
|
|
Write = 1'b1;
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b11000110,8'b11001110,8'b11010110,8'b11011110,8'b11100110,8'b11101110,8'b11110110,8'b11111110
|
|
|
|
8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,
|
|
8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001111,
|
|
8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010111,
|
|
8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011111,
|
|
8'b10100000,8'b10100001,8'b10100010,8'b10100011,8'b10100100,8'b10100101,8'b10100111,
|
|
8'b10101000,8'b10101001,8'b10101010,8'b10101011,8'b10101100,8'b10101101,8'b10101111,
|
|
8'b10110000,8'b10110001,8'b10110010,8'b10110011,8'b10110100,8'b10110101,8'b10110111,
|
|
8'b10111000,8'b10111001,8'b10111010,8'b10111011,8'b10111100,8'b10111101,8'b10111111 :
|
|
begin
|
|
// RES b,r
|
|
if (MCycle == 3'b001 )
|
|
begin
|
|
ALU_Op = 4'b1011;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
end
|
|
end // case: 8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000111,...
|
|
|
|
8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110 :
|
|
begin
|
|
// RES b,(HL)
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 , 7 :
|
|
Set_Addr_To = aXY;
|
|
2 :
|
|
begin
|
|
ALU_Op = 4'b1011;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
Set_Addr_To = aXY;
|
|
TStates = 3'b100;
|
|
end
|
|
|
|
3 :
|
|
Write = 1'b1;
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b10000110,8'b10001110,8'b10010110,8'b10011110,8'b10100110,8'b10101110,8'b10110110,8'b10111110
|
|
|
|
endcase // case(IRB)
|
|
end // case: 2'b01
|
|
|
|
|
|
default :
|
|
begin : default_ed_block
|
|
|
|
//----------------------------------------------------------------------------
|
|
//
|
|
// ED prefixed instructions
|
|
//
|
|
//----------------------------------------------------------------------------
|
|
|
|
case (IRB)
|
|
8'b00000000,8'b00000001,8'b00000010,8'b00000011,8'b00000100,8'b00000101,8'b00000110,8'b00000111
|
|
,8'b00001000,8'b00001001,8'b00001010,8'b00001011,8'b00001100,8'b00001101,8'b00001110,8'b00001111
|
|
,8'b00010000,8'b00010001,8'b00010010,8'b00010011,8'b00010100,8'b00010101,8'b00010110,8'b00010111
|
|
,8'b00011000,8'b00011001,8'b00011010,8'b00011011,8'b00011100,8'b00011101,8'b00011110,8'b00011111
|
|
,8'b00100000,8'b00100001,8'b00100010,8'b00100011,8'b00100100,8'b00100101,8'b00100110,8'b00100111
|
|
,8'b00101000,8'b00101001,8'b00101010,8'b00101011,8'b00101100,8'b00101101,8'b00101110,8'b00101111
|
|
,8'b00110000,8'b00110001,8'b00110010,8'b00110011,8'b00110100,8'b00110101,8'b00110110,8'b00110111
|
|
,8'b00111000,8'b00111001,8'b00111010,8'b00111011,8'b00111100,8'b00111101,8'b00111110,8'b00111111
|
|
|
|
|
|
,8'b10000000,8'b10000001,8'b10000010,8'b10000011,8'b10000100,8'b10000101,8'b10000110,8'b10000111
|
|
,8'b10001000,8'b10001001,8'b10001010,8'b10001011,8'b10001100,8'b10001101,8'b10001110,8'b10001111
|
|
,8'b10010000,8'b10010001,8'b10010010,8'b10010011,8'b10010100,8'b10010101,8'b10010110,8'b10010111
|
|
,8'b10011000,8'b10011001,8'b10011010,8'b10011011,8'b10011100,8'b10011101,8'b10011110,8'b10011111
|
|
, 8'b10100100,8'b10100101,8'b10100110,8'b10100111
|
|
, 8'b10101100,8'b10101101,8'b10101110,8'b10101111
|
|
, 8'b10110100,8'b10110101,8'b10110110,8'b10110111
|
|
, 8'b10111100,8'b10111101,8'b10111110,8'b10111111
|
|
,8'b11000000,8'b11000001,8'b11000010,8'b11000011,8'b11000100,8'b11000101,8'b11000110,8'b11000111
|
|
,8'b11001000,8'b11001001,8'b11001010,8'b11001011,8'b11001100,8'b11001101,8'b11001110,8'b11001111
|
|
,8'b11010000,8'b11010001,8'b11010010,8'b11010011,8'b11010100,8'b11010101,8'b11010110,8'b11010111
|
|
,8'b11011000,8'b11011001,8'b11011010,8'b11011011,8'b11011100,8'b11011101,8'b11011110,8'b11011111
|
|
,8'b11100000,8'b11100001,8'b11100010,8'b11100011,8'b11100100,8'b11100101,8'b11100110,8'b11100111
|
|
,8'b11101000,8'b11101001,8'b11101010,8'b11101011,8'b11101100,8'b11101101,8'b11101110,8'b11101111
|
|
,8'b11110000,8'b11110001,8'b11110010,8'b11110011,8'b11110100,8'b11110101,8'b11110110,8'b11110111
|
|
,8'b11111000,8'b11111001,8'b11111010,8'b11111011,8'b11111100,8'b11111101,8'b11111110,8'b11111111 :
|
|
; // NOP, undocumented
|
|
|
|
8'b01111110,8'b01111111 :
|
|
// NOP, undocumented
|
|
;
|
|
// 8 BIT LOAD GROUP
|
|
8'b01010111 :
|
|
begin
|
|
// LD A,I
|
|
Special_LD = 3'b100;
|
|
TStates = 3'b101;
|
|
end
|
|
|
|
8'b01011111 :
|
|
begin
|
|
// LD A,R
|
|
Special_LD = 3'b101;
|
|
TStates = 3'b101;
|
|
end
|
|
|
|
8'b01000111 :
|
|
begin
|
|
// LD I,A
|
|
Special_LD = 3'b110;
|
|
TStates = 3'b101;
|
|
end
|
|
|
|
8'b01001111 :
|
|
begin
|
|
// LD R,A
|
|
Special_LD = 3'b111;
|
|
TStates = 3'b101;
|
|
end
|
|
|
|
// 16 BIT LOAD GROUP
|
|
8'b01001011,8'b01011011,8'b01101011,8'b01111011 :
|
|
begin
|
|
// LD dd,(nn)
|
|
MCycles = 3'b101;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Set_Addr_To = aZI;
|
|
Inc_PC = 1'b1;
|
|
LDW = 1'b1;
|
|
end
|
|
|
|
4 :
|
|
begin
|
|
Read_To_Reg = 1'b1;
|
|
if (IR[5:4] == 2'b11 )
|
|
begin
|
|
Set_BusA_To = 4'b1000;
|
|
end
|
|
else
|
|
begin
|
|
Set_BusA_To[2:1] = IR[5:4];
|
|
Set_BusA_To[0] = 1'b1;
|
|
end
|
|
Inc_WZ = 1'b1;
|
|
Set_Addr_To = aZI;
|
|
end // case: 4
|
|
|
|
5 :
|
|
begin
|
|
Read_To_Reg = 1'b1;
|
|
if (IR[5:4] == 2'b11 )
|
|
begin
|
|
Set_BusA_To = 4'b1001;
|
|
end
|
|
else
|
|
begin
|
|
Set_BusA_To[2:1] = IR[5:4];
|
|
Set_BusA_To[0] = 1'b0;
|
|
end
|
|
end // case: 5
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b01001011,8'b01011011,8'b01101011,8'b01111011
|
|
|
|
|
|
8'b01000011,8'b01010011,8'b01100011,8'b01110011 :
|
|
begin
|
|
// LD (nn),dd
|
|
MCycles = 3'b101;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
LDZ = 1'b1;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Set_Addr_To = aZI;
|
|
Inc_PC = 1'b1;
|
|
LDW = 1'b1;
|
|
if (IR[5:4] == 2'b11 )
|
|
begin
|
|
Set_BusB_To = 4'b1000;
|
|
end
|
|
else
|
|
begin
|
|
Set_BusB_To[2:1] = IR[5:4];
|
|
Set_BusB_To[0] = 1'b1;
|
|
Set_BusB_To[3] = 1'b0;
|
|
end
|
|
end // case: 3
|
|
|
|
4 :
|
|
begin
|
|
Inc_WZ = 1'b1;
|
|
Set_Addr_To = aZI;
|
|
Write = 1'b1;
|
|
if (IR[5:4] == 2'b11 )
|
|
begin
|
|
Set_BusB_To = 4'b1001;
|
|
end
|
|
else
|
|
begin
|
|
Set_BusB_To[2:1] = IR[5:4];
|
|
Set_BusB_To[0] = 1'b0;
|
|
Set_BusB_To[3] = 1'b0;
|
|
end
|
|
end // case: 4
|
|
|
|
5 :
|
|
begin
|
|
Write = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b01000011,8'b01010011,8'b01100011,8'b01110011
|
|
|
|
8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000 :
|
|
begin
|
|
// LDI, LDD, LDIR, LDDR
|
|
MCycles = 3'b100;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
Set_Addr_To = aXY;
|
|
IncDec_16 = 4'b1100; // BC
|
|
end
|
|
|
|
2 :
|
|
begin
|
|
Set_BusB_To = 4'b0110;
|
|
Set_BusA_To[2:0] = 3'b111;
|
|
ALU_Op = 4'b0000;
|
|
Set_Addr_To = aDE;
|
|
if (IR[3] == 1'b0 )
|
|
begin
|
|
IncDec_16 = 4'b0110; // IX
|
|
end
|
|
else
|
|
begin
|
|
IncDec_16 = 4'b1110;
|
|
end
|
|
end // case: 2
|
|
|
|
3 :
|
|
begin
|
|
I_BT = 1'b1;
|
|
TStates = 3'b101;
|
|
Write = 1'b1;
|
|
if (IR[3] == 1'b0 )
|
|
begin
|
|
IncDec_16 = 4'b0101; // DE
|
|
end
|
|
else
|
|
begin
|
|
IncDec_16 = 4'b1101;
|
|
end
|
|
end // case: 3
|
|
|
|
4 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
TStates = 3'b101;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b10100000 , 8'b10101000 , 8'b10110000 , 8'b10111000
|
|
|
|
8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001 :
|
|
begin
|
|
// CPI, CPD, CPIR, CPDR
|
|
MCycles = 3'b100;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
Set_Addr_To = aXY;
|
|
IncDec_16 = 4'b1100; // BC
|
|
end
|
|
|
|
2 :
|
|
begin
|
|
Set_BusB_To = 4'b0110;
|
|
Set_BusA_To[2:0] = 3'b111;
|
|
ALU_Op = 4'b0111;
|
|
Save_ALU = 1'b1;
|
|
PreserveC = 1'b1;
|
|
if (IR[3] == 1'b0 )
|
|
begin
|
|
IncDec_16 = 4'b0110;
|
|
end
|
|
else
|
|
begin
|
|
IncDec_16 = 4'b1110;
|
|
end
|
|
end // case: 2
|
|
|
|
3 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
I_BC = 1'b1;
|
|
TStates = 3'b101;
|
|
end
|
|
|
|
4 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
TStates = 3'b101;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b10100001 , 8'b10101001 , 8'b10110001 , 8'b10111001
|
|
|
|
8'b01000100,8'b01001100,8'b01010100,8'b01011100,8'b01100100,8'b01101100,8'b01110100,8'b01111100 :
|
|
begin
|
|
// NEG
|
|
ALU_Op = 4'b0010;
|
|
Set_BusB_To = 4'b0111;
|
|
Set_BusA_To = 4'b1010;
|
|
Read_To_Acc = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
end
|
|
|
|
8'b01000110,8'b01001110,8'b01100110,8'b01101110 :
|
|
begin
|
|
// IM 0
|
|
IMode = 2'b00;
|
|
end
|
|
|
|
8'b01010110,8'b01110110 :
|
|
// IM 1
|
|
IMode = 2'b01;
|
|
|
|
8'b01011110,8'b01110111 :
|
|
// IM 2
|
|
IMode = 2'b10;
|
|
|
|
// 16 bit arithmetic
|
|
8'b01001010,8'b01011010,8'b01101010,8'b01111010 :
|
|
begin
|
|
// ADC HL,ss
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
ALU_Op = 4'b0001;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
Set_BusA_To[2:0] = 3'b101;
|
|
case (IR[5:4])
|
|
0,1,2 :
|
|
begin
|
|
Set_BusB_To[2:1] = IR[5:4];
|
|
Set_BusB_To[0] = 1'b1;
|
|
end
|
|
default :
|
|
Set_BusB_To = 4'b1000;
|
|
endcase
|
|
TStates = 3'b100;
|
|
end // case: 2
|
|
|
|
3 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
ALU_Op = 4'b0001;
|
|
Set_BusA_To[2:0] = 3'b100;
|
|
case (IR[5:4])
|
|
0,1,2 :
|
|
begin
|
|
Set_BusB_To[2:1] = IR[5:4];
|
|
Set_BusB_To[0] = 1'b0;
|
|
end
|
|
default :
|
|
Set_BusB_To = 4'b1001;
|
|
endcase // case(IR[5:4])
|
|
end // case: 3
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b01001010,8'b01011010,8'b01101010,8'b01111010
|
|
|
|
8'b01000010,8'b01010010,8'b01100010,8'b01110010 :
|
|
begin
|
|
// SBC HL,ss
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
ALU_Op = 4'b0011;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
Set_BusA_To[2:0] = 3'b101;
|
|
case (IR[5:4])
|
|
0,1,2 :
|
|
begin
|
|
Set_BusB_To[2:1] = IR[5:4];
|
|
Set_BusB_To[0] = 1'b1;
|
|
end
|
|
default :
|
|
Set_BusB_To = 4'b1000;
|
|
endcase
|
|
TStates = 3'b100;
|
|
end // case: 2
|
|
|
|
3 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
ALU_Op = 4'b0011;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
Set_BusA_To[2:0] = 3'b100;
|
|
case (IR[5:4])
|
|
0,1,2 :
|
|
Set_BusB_To[2:1] = IR[5:4];
|
|
default :
|
|
Set_BusB_To = 4'b1001;
|
|
endcase
|
|
end // case: 3
|
|
|
|
default :;
|
|
|
|
endcase // case(MCycle)
|
|
end // case: 8'b01000010,8'b01010010,8'b01100010,8'b01110010
|
|
|
|
8'b01101111 :
|
|
begin
|
|
// RLD
|
|
MCycles = 3'b100;
|
|
case (MCycle)
|
|
2 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
Set_Addr_To = aXY;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Read_To_Reg = 1'b1;
|
|
Set_BusB_To[2:0] = 3'b110;
|
|
Set_BusA_To[2:0] = 3'b111;
|
|
ALU_Op = 4'b1101;
|
|
TStates = 3'b100;
|
|
Set_Addr_To = aXY;
|
|
Save_ALU = 1'b1;
|
|
end
|
|
|
|
4 :
|
|
begin
|
|
I_RLD = 1'b1;
|
|
Write = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b01101111
|
|
|
|
8'b01100111 :
|
|
begin
|
|
// RRD
|
|
MCycles = 3'b100;
|
|
case (MCycle)
|
|
2 :
|
|
Set_Addr_To = aXY;
|
|
3 :
|
|
begin
|
|
Read_To_Reg = 1'b1;
|
|
Set_BusB_To[2:0] = 3'b110;
|
|
Set_BusA_To[2:0] = 3'b111;
|
|
ALU_Op = 4'b1110;
|
|
TStates = 3'b100;
|
|
Set_Addr_To = aXY;
|
|
Save_ALU = 1'b1;
|
|
end
|
|
|
|
4 :
|
|
begin
|
|
I_RRD = 1'b1;
|
|
Write = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b01100111
|
|
|
|
8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101 :
|
|
begin
|
|
// RETI, RETN
|
|
MCycles = 3'b011;
|
|
case (MCycle)
|
|
1 :
|
|
Set_Addr_To = aSP;
|
|
|
|
2 :
|
|
begin
|
|
IncDec_16 = 4'b0111;
|
|
Set_Addr_To = aSP;
|
|
LDZ = 1'b1;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
Jump = 1'b1;
|
|
IncDec_16 = 4'b0111;
|
|
I_RETN = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b01000101,8'b01001101,8'b01010101,8'b01011101,8'b01100101,8'b01101101,8'b01110101,8'b01111101
|
|
|
|
8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000 :
|
|
begin
|
|
// IN r,(C)
|
|
MCycles = 3'b010;
|
|
case (MCycle)
|
|
1 :
|
|
Set_Addr_To = aBC;
|
|
|
|
2 :
|
|
begin
|
|
IORQ = 1'b1;
|
|
if (IR[5:3] != 3'b110 )
|
|
begin
|
|
Read_To_Reg = 1'b1;
|
|
Set_BusA_To[2:0] = IR[5:3];
|
|
end
|
|
I_INRC = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b01000000,8'b01001000,8'b01010000,8'b01011000,8'b01100000,8'b01101000,8'b01110000,8'b01111000
|
|
|
|
8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001 :
|
|
begin
|
|
// OUT (C),r
|
|
// OUT (C),0
|
|
MCycles = 3'b010;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
Set_Addr_To = aBC;
|
|
Set_BusB_To[2:0] = IR[5:3];
|
|
if (IR[5:3] == 3'b110 )
|
|
begin
|
|
Set_BusB_To[3] = 1'b1;
|
|
end
|
|
end
|
|
|
|
2 :
|
|
begin
|
|
Write = 1'b1;
|
|
IORQ = 1'b1;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b01000001,8'b01001001,8'b01010001,8'b01011001,8'b01100001,8'b01101001,8'b01110001,8'b01111001
|
|
|
|
8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010 :
|
|
begin
|
|
// INI, IND, INIR, INDR
|
|
MCycles = 3'b100;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
Set_Addr_To = aBC;
|
|
Set_BusB_To = 4'b1010;
|
|
Set_BusA_To = 4'b0000;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
ALU_Op = 4'b0010;
|
|
end
|
|
|
|
2 :
|
|
begin
|
|
IORQ = 1'b1;
|
|
Set_BusB_To = 4'b0110;
|
|
Set_Addr_To = aXY;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
if (IR[3] == 1'b0 )
|
|
begin
|
|
IncDec_16 = 4'b0010;
|
|
end
|
|
else
|
|
begin
|
|
IncDec_16 = 4'b1010;
|
|
end
|
|
TStates = 3'b100;
|
|
Write = 1'b1;
|
|
I_BTR = 1'b1;
|
|
end // case: 3
|
|
|
|
4 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
TStates = 3'b101;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b10100010 , 8'b10101010 , 8'b10110010 , 8'b10111010
|
|
|
|
8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011 :
|
|
begin
|
|
// OUTI, OUTD, OTIR, OTDR
|
|
MCycles = 3'b100;
|
|
case (MCycle)
|
|
1 :
|
|
begin
|
|
TStates = 3'b101;
|
|
Set_Addr_To = aXY;
|
|
Set_BusB_To = 4'b1010;
|
|
Set_BusA_To = 4'b0000;
|
|
Read_To_Reg = 1'b1;
|
|
Save_ALU = 1'b1;
|
|
ALU_Op = 4'b0010;
|
|
end
|
|
|
|
2 :
|
|
begin
|
|
Set_BusB_To = 4'b0110;
|
|
Set_Addr_To = aBC;
|
|
end
|
|
|
|
3 :
|
|
begin
|
|
if (IR[3] == 1'b0 )
|
|
begin
|
|
IncDec_16 = 4'b0010;
|
|
end
|
|
else
|
|
begin
|
|
IncDec_16 = 4'b1010;
|
|
end
|
|
IORQ = 1'b1;
|
|
Write = 1'b1;
|
|
I_BTR = 1'b1;
|
|
end // case: 3
|
|
|
|
4 :
|
|
begin
|
|
NoRead = 1'b1;
|
|
TStates = 3'b101;
|
|
end
|
|
|
|
default :;
|
|
endcase // case(MCycle)
|
|
end // case: 8'b10100011 , 8'b10101011 , 8'b10110011 , 8'b10111011
|
|
|
|
endcase // case(IRB)
|
|
end // block: default_ed_block
|
|
endcase // case(ISet)
|
|
|
|
if (Mode == 1 )
|
|
begin
|
|
if (MCycle == 3'b001 )
|
|
begin
|
|
//TStates = 3'b100;
|
|
end
|
|
else
|
|
begin
|
|
TStates = 3'b011;
|
|
end
|
|
end
|
|
|
|
if (Mode == 3 )
|
|
begin
|
|
if (MCycle == 3'b001 )
|
|
begin
|
|
//TStates = 3'b100;
|
|
end
|
|
else
|
|
begin
|
|
TStates = 3'b100;
|
|
end
|
|
end
|
|
|
|
if (Mode < 2 )
|
|
begin
|
|
if (MCycle == 3'b110 )
|
|
begin
|
|
Inc_PC = 1'b1;
|
|
if (Mode == 1 )
|
|
begin
|
|
Set_Addr_To = aXY;
|
|
TStates = 3'b100;
|
|
Set_BusB_To[2:0] = SSS;
|
|
Set_BusB_To[3] = 1'b0;
|
|
end
|
|
if (IRB == 8'b00110110 || IRB == 8'b11001011 )
|
|
begin
|
|
Set_Addr_To = aNone;
|
|
end
|
|
end
|
|
if (MCycle == 3'b111 )
|
|
begin
|
|
if (Mode == 0 )
|
|
begin
|
|
TStates = 3'b101;
|
|
end
|
|
if (ISet != 2'b01 )
|
|
begin
|
|
Set_Addr_To = aXY;
|
|
end
|
|
Set_BusB_To[2:0] = SSS;
|
|
Set_BusB_To[3] = 1'b0;
|
|
if (IRB == 8'b00110110 || ISet == 2'b01 )
|
|
begin
|
|
// LD (HL),n
|
|
Inc_PC = 1'b1;
|
|
end
|
|
else
|
|
begin
|
|
NoRead = 1'b1;
|
|
end
|
|
end
|
|
end // if (Mode < 2 )
|
|
|
|
end // always @ (IR, ISet, MCycle, F, NMICycle, IntCycle)
|
|
|
|
// synopsys dc_script_begin
|
|
// set_attribute current_design "revision" "$Id: tv80_mcode.v,v 1.1 2004/05/16 17:39:57 ghutchis Exp $" -type string -quiet
|
|
// synopsys dc_script_end
|
|
endmodule // T80_MCode
|
|
|
|
|
|
|