184 lines
5.6 KiB
Verilog
184 lines
5.6 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE AC 97 Controller ////
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//// Serial Output Block ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: ac97_sout.v,v 1.2 2002/09/19 06:30:56 rudi Exp $
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//
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// $Date: 2002/09/19 06:30:56 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: ac97_sout.v,v $
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// Revision 1.2 2002/09/19 06:30:56 rudi
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// Fixed a bug reported by Igor. Apparently this bug only shows up when
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// the WB clock is very low (2x bit_clk). Updated Copyright header.
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//
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// Revision 1.1 2001/08/03 06:54:50 rudi
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//
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//
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// - Changed to new directory structure
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//
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// Revision 1.1.1.1 2001/05/19 02:29:15 rudi
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// Initial Checkin
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//
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//
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//
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//
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`include "ac97_defines.v"
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module ac97_sout(clk, rst,
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so_ld, slt0, slt1, slt2, slt3, slt4,
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slt6, slt7, slt8, slt9,
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sdata_out
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);
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input clk, rst;
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// --------------------------------------
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// Misc Signals
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input so_ld;
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input [15:0] slt0;
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input [19:0] slt1;
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input [19:0] slt2;
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input [19:0] slt3;
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input [19:0] slt4;
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input [19:0] slt6;
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input [19:0] slt7;
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input [19:0] slt8;
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input [19:0] slt9;
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// --------------------------------------
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// AC97 Codec Interface
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output sdata_out;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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wire sdata_out;
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reg [15:0] slt0_r;
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reg [19:0] slt1_r;
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reg [19:0] slt2_r;
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reg [19:0] slt3_r;
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reg [19:0] slt4_r;
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reg [19:0] slt5_r;
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reg [19:0] slt6_r;
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reg [19:0] slt7_r;
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reg [19:0] slt8_r;
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reg [19:0] slt9_r;
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reg [19:0] slt10_r;
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reg [19:0] slt11_r;
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reg [19:0] slt12_r;
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////////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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////////////////////////////////////////////////////////////////////
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//
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// Serial Shift Register
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//
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assign sdata_out = slt0_r[15];
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always @(posedge clk)
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if(so_ld) slt0_r <= #1 slt0;
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else slt0_r <= #1 {slt0_r[14:0], slt1_r[19]};
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always @(posedge clk)
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if(so_ld) slt1_r <= #1 slt1;
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else slt1_r <= #1 {slt1_r[18:0], slt2_r[19]};
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always @(posedge clk)
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if(so_ld) slt2_r <= #1 slt2;
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else slt2_r <= #1 {slt2_r[18:0], slt3_r[19]};
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always @(posedge clk)
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if(so_ld) slt3_r <= #1 slt3;
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else slt3_r <= #1 {slt3_r[18:0], slt4_r[19]};
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always @(posedge clk)
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if(so_ld) slt4_r <= #1 slt4;
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else slt4_r <= #1 {slt4_r[18:0], slt5_r[19]};
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always @(posedge clk)
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if(so_ld) slt5_r <= #1 20'h0;
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else slt5_r <= #1 {slt5_r[18:0], slt6_r[19]};
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always @(posedge clk)
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if(so_ld) slt6_r <= #1 slt6;
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else slt6_r <= #1 {slt6_r[18:0], slt7_r[19]};
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always @(posedge clk)
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if(so_ld) slt7_r <= #1 slt7;
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else slt7_r <= #1 {slt7_r[18:0], slt8_r[19]};
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always @(posedge clk)
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if(so_ld) slt8_r <= #1 slt8;
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else slt8_r <= #1 {slt8_r[18:0], slt9_r[19]};
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always @(posedge clk)
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if(so_ld) slt9_r <= #1 slt9;
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else slt9_r <= #1 {slt9_r[18:0], slt10_r[19]};
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always @(posedge clk)
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if(so_ld) slt10_r <= #1 20'h0;
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else slt10_r <= #1 {slt10_r[18:0], slt11_r[19]};
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always @(posedge clk)
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if(so_ld) slt11_r <= #1 20'h0;
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else slt11_r <= #1 {slt11_r[18:0], slt12_r[19]};
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always @(posedge clk)
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if(so_ld) slt12_r <= #1 20'h0;
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else slt12_r <= #1 {slt12_r[18:0], 1'b0 };
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endmodule
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