174 lines
7.2 KiB
Verilog
174 lines
7.2 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE AC 97 Controller Definitions ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: ac97_defines.v,v 1.5 2002/09/19 06:30:56 rudi Exp $
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//
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// $Date: 2002/09/19 06:30:56 $
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// $Revision: 1.5 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: ac97_defines.v,v $
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// Revision 1.5 2002/09/19 06:30:56 rudi
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// Fixed a bug reported by Igor. Apparently this bug only shows up when
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// the WB clock is very low (2x bit_clk). Updated Copyright header.
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//
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// Revision 1.4 2002/03/11 03:21:22 rudi
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//
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// - Added defines to select fifo depth between 4, 8 and 16 entries.
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//
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// Revision 1.3 2002/03/05 04:44:05 rudi
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//
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// - Fixed the order of the thrash hold bits to match the spec.
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// - Many minor synthesis cleanup items ...
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//
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// Revision 1.2 2001/08/10 08:09:42 rudi
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//
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// - Removed RTY_O output.
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// - Added Clock and Reset Inputs to documentation.
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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//
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// Revision 1.1 2001/08/03 06:54:49 rudi
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//
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//
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// - Changed to new directory structure
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//
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// Revision 1.1.1.1 2001/05/19 02:29:14 rudi
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// Initial Checkin
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//
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//
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//
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//
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`timescale 1ns / 10ps
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/////////////////////////////////////////////////////////////////////
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// This AC97 Controller supports up to 6 Output and 3 Input Channels.
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// Comment out the define statement for which channels you do not wish
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// to support in your implementation. The main Left and Right channels
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// are always supported.
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// Surround Left + Right
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`define AC97_SURROUND 1
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// Center Channel
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`define AC97_CENTER 1
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// LFE Channel
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`define AC97_LFE 1
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// Stereo Input
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`define AC97_SIN 1
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// Mono Microphone Input
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`define AC97_MICIN 1
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/////////////////////////////////////////////////////////////////////
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//
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// This define selects how the WISHBONE interface determines if
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// the internal register file is selected.
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// This should be a simple address decoder. "wb_addr_i" is the
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// WISHBONE address bus (32 bits wide).
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`define AC97_REG_SEL (wb_addr_i[31:29] == 3'h0)
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/////////////////////////////////////////////////////////////////////
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//
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// This is a prescaler that generates a pulse every 250 nS.
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// The value here should one less than the actually calculated
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// value.
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// For a 200 MHz wishbone clock, this value is 49 (50-1).
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`define AC97_250_PS 6'h31
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/////////////////////////////////////////////////////////////////////
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//
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// AC97 Cold reset Must be asserted for at least 1uS. The AC97
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// controller will stretch the reset pulse to at least 1uS.
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// The reset timer is driven by the AC97_250_PS prescaler.
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// This value should probably be never changed. Adjust the
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// AC97_250_PS instead.
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`define AC97_RST_DEL 3'h4
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/////////////////////////////////////////////////////////////////////
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//
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// This value indicates for how long the resume signaling (asserting sync)
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// should be done. This counter is driven by the AC97_250_PS prescaler.
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// This value times 250nS is the duration of the resume signaling.
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// The actual value must be incremented by one, as we do not know
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// the current state of the prescaler, and must somehow insure we
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// meet the minimum 1uS length. This value should probably be never
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// changed. Modify the AC97_250_PS instead.
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`define AC97_RES_SIG 3'h5
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/////////////////////////////////////////////////////////////////////
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//
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// If the bit clock is absent for at least two "predicted" bit
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// clock periods (163 nS) we should signal "suspended".
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// This value defines how many WISHBONE cycles must pass without
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// any change on the bit clock input before we signal "suspended".
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// For a 200 MHz WISHBONE clock this would be about (163/5) 33 cycles.
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`define AC97_SUSP_DET 6'h21
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/////////////////////////////////////////////////////////////////////
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//
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// Select FIFO Depth. For most applications a FIFO depth of 4 should
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// be sufficient. For systems with slow interrupt processing or slow
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// DMA response or systems with low internal bus bandwidth you might
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// want to increase the FIFO sizes to reduce the interrupt/DMA service
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// request frequencies.
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// Service request frequency can be calculated as follows:
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// Channel bandwidth / FIFO size = Service Request Frequency
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// For Example: 48KHz / 4 = 12 kHz
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//
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// Select Input FIFO depth by uncommenting ONE of the following define
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// statements:
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`define AC97_IN_FIFO_DEPTH_4
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//`define AC97_IN_FIFO_DEPTH_8
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//`define AC97_IN_FIFO_DEPTH_16
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//
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// Select Output FIFO depth by uncommenting ONE of the following define
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// statements:
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`define AC97_OUT_FIFO_DEPTH_4
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//`define AC97_OUT_FIFO_DEPTH_8
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//`define AC97_OUT_FIFO_DEPTH_16
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