OpenFPGA/openfpga_flow/openfpga_cell_library/verilog
tangxifan c036c87d6d [HDL] Bug fix in the GP output pad 2020-11-02 18:37:53 -07:00
..
adder.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
aib.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
dff.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
dpram.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
dpram1k.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
dpram16k.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
frac_mem_32k.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
gpio.v [HDL] Bug fix in the GP output pad 2020-11-02 18:37:53 -07:00
latch.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
lut6.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
mult_32x32.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
mult_36x36.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
mux2.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
sram.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00