tangxifan ae899f3b11 bug fixed for clock names		2020-02-27 16:51:55 -07:00
..
src	bug fixed for clock names	2020-02-27 16:51:55 -07:00
test_blif	use a micro benchmark for vpr quick-run	2020-01-26 17:56:22 -07:00
test_openfpga_arch	bug fixing for lb router. Add physical mode to default node expanding settings	2020-02-21 11:29:00 -07:00
test_script	debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports	2020-02-27 13:24:26 -07:00
test_vpr_arch	bug fixing for lb router. Add physical mode to default node expanding settings	2020-02-21 11:29:00 -07:00
CMakeLists.txt	start implement openfpga shell and use vpr as a macro	2020-01-22 20:20:10 -07:00