tangxifan 906191e931 [Architecture] Use strict latch Verilog HDL in frame-based procotol		2020-09-23 17:58:13 -06:00
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configuration_chain/config	enrich basic regression tests to cover more critical microbenchmarks	2020-07-27 19:47:43 -06:00
configuration_frame/config	enrich basic regression tests to cover more critical microbenchmarks	2020-07-27 19:47:43 -06:00
configuration_frame_ccff/config	[Architecture] Use strict latch Verilog HDL in frame-based procotol	2020-09-23 17:58:13 -06:00
configuration_frame_resetb/config	[Regression Test] Add test case for configurable latch with active-low reset	2020-09-23 17:25:17 -06:00
fast_configuration_chain/config	enrich basic regression tests to cover more critical microbenchmarks	2020-07-27 19:47:43 -06:00
fast_configuration_frame/config	enrich basic regression tests to cover more critical microbenchmarks	2020-07-27 19:47:43 -06:00
fast_memory_bank/config	enrich basic regression tests to cover more critical microbenchmarks	2020-07-27 19:47:43 -06:00
flatten_memory/config	enrich basic regression tests to cover more critical microbenchmarks	2020-07-27 19:47:43 -06:00
memory_bank/config	enrich basic regression tests to cover more critical microbenchmarks	2020-07-27 19:47:43 -06:00