101 lines
1.8 KiB
Verilog
101 lines
1.8 KiB
Verilog
module SAPone(
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output wire [7:0] SAP_out,
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output wire [11:0] con,
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output reg [7:0] bus,
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input clk,
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input clr_
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);
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wire cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_;
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wire [7:0] acc_out2, BRegister_out, OutputRegister_out;
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wire [3:0] IR_out, mar_out;
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wire [4:0] bus_sel;
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wire [3:0] pc_out, oprand;
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wire [7:0] rom_out, acc_out1, ADDSUB_out;
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assign {cp, ep, lm_, ce_, li_, ei_, la_, ea, su, eu, lb_, lo_} = con;
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assign bus_sel = {ep, ce_, ei_, ea, eu};
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always@(*)
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begin
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case(bus_sel)
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5'b11100: bus[3:0] = pc_out;
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5'b00100: bus[7:0] = rom_out;
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5'b01000: bus[3:0] = oprand;
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5'b01110: bus[7:0] = acc_out1;
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5'b01101: bus[7:0] = ADDSUB_out;
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default: bus[7:0] = 8'bx;
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endcase
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end
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PC pc1(
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.pc_out(pc_out),
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.cp(cp),
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.clk(clk),
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.clr_(clr_)
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);
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MAR mar1(
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.mar_out(mar_out),
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.mar_in(bus[3:0]),
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.lm_(lm_),
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.clk(clk),
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.clr_(clr_)
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);
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ROM roml(
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.rom_out(rom_out),
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.rom_in(mar_out)
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);
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IR ir1(
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.opcode(IR_out),
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.oprand(oprand),
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.IR_in(bus[7:0]),
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.li_(li_),
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.clk(clk),
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.clr_(clr_)
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);
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Controller cont1(
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.control_signals(con),
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.opcode(IR_out),
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.clk(clk),
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.clr_(clr_)
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);
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ACC acc1(
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.acc_out1(acc_out1),
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.acc_out2(acc_out2),
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.acc_in(bus[7:0]),
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.la_(la_),
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.clk(clk),
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.clr_(clr_)
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);
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ADDSUB addsub1(
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.ADDSUB_out(ADDSUB_out),
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.ADDSUB_in1(acc_out2),
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.ADDSUB_in2(BRegister_out),
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.su(su)
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);
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BRegister bregister1(
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.BRegister_out(BRegister_out),
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.BRegister_in(bus[7:0]),
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.lb_(lb_),
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.clk(clk),
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.clr_(clr_)
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);
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OutputRegister outputregister1(
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.OutputRegister_out(SAP_out),
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.OutputRegister_in(bus[7:0]),
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.lo_(lo_),
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.clk(clk),
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.clr_(clr_)
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);
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endmodule
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