592 lines
18 KiB
Verilog
592 lines
18 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant VGA/LCD Core; Pixel Generator ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: vga_pgen.v,v 1.7 2003/08/01 11:46:38 rherveille Exp $
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//
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// $Date: 2003/08/01 11:46:38 $
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// $Revision: 1.7 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: vga_pgen.v,v $
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// Revision 1.7 2003/08/01 11:46:38 rherveille
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// 1) Rewrote vga_fifo_dc. It now uses gray codes and a more elaborate anti-metastability scheme.
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// 2) Changed top level and pixel generator to reflect changes in the fifo.
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// 3) Changed a bug in vga_fifo.
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// 4) Changed pixel generator and wishbone master to reflect changes.
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//
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// Revision 1.6 2003/05/07 09:48:54 rherveille
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// Fixed some Wishbone RevB.3 related bugs.
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// Changed layout of the core. Blocks are located more logically now.
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// Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.
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//
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// Revision 1.5 2002/04/05 06:24:35 rherveille
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// Fixed a potential reset bug in the hint & vint generation.
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//
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// Revision 1.4 2002/01/28 03:47:16 rherveille
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// Changed counter-library.
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// Changed vga-core.
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// Added 32bpp mode.
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//
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//synopsys translate_off
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`include "timescale.v"
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//synopsys translate_on
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`include "vga_defines.v"
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module vga_pgen (
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clk_i, ctrl_ven, ctrl_HSyncL, Thsync, Thgdel, Thgate, Thlen,
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ctrl_VSyncL, Tvsync, Tvgdel, Tvgate, Tvlen, ctrl_CSyncL, ctrl_BlankL,
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eoh, eov,
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ctrl_dvi_odf, ctrl_cd, ctrl_pc,
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fb_data_fifo_rreq, fb_data_fifo_empty, fb_data_fifo_q, ImDoneFifoQ,
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stat_acmp, clut_req, clut_adr, clut_q, clut_ack, ctrl_cbsw, clut_switch,
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cursor_adr,
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cursor0_en, cursor0_res, cursor0_xy, cc0_adr_o, cc0_dat_i,
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cursor1_en, cursor1_res, cursor1_xy, cc1_adr_o, cc1_dat_i,
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line_fifo_wreq, line_fifo_full, line_fifo_d, line_fifo_rreq, line_fifo_q,
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pclk_i,
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`ifdef VGA_12BIT_DVI
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dvi_pclk_p_o, dvi_pclk_m_o, dvi_hsync_o, dvi_vsync_o, dvi_de_o, dvi_d_o,
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`endif
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pclk_o, hsync_o, vsync_o, csync_o, blank_o, r_o, g_o, b_o
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);
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// inputs & outputs
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input clk_i; // master clock
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input ctrl_ven; // Video enable signal
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// horiontal timing settings
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input ctrl_HSyncL; // horizontal sync pulse polarization level (pos/neg)
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input [ 7:0] Thsync; // horizontal sync pulse width (in pixels)
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input [ 7:0] Thgdel; // horizontal gate delay (in pixels)
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input [15:0] Thgate; // horizontal gate length (number of visible pixels per line)
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input [15:0] Thlen; // horizontal length (number of pixels per line)
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// vertical timing settings
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input ctrl_VSyncL; // vertical sync pulse polarization level (pos/neg)
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input [ 7:0] Tvsync; // vertical sync pulse width (in lines)
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input [ 7:0] Tvgdel; // vertical gate delay (in lines)
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input [15:0] Tvgate; // vertical gate length (number of visible lines in frame)
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input [15:0] Tvlen; // vertical length (number of lines in frame)
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// composite signals
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input ctrl_CSyncL; // composite sync pulse polarization level
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input ctrl_BlankL; // blank signal polarization level
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// status outputs
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output eoh; // end of horizontal
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reg eoh;
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output eov; // end of vertical;
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reg eov;
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// Pixel signals
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input [ 1: 0] ctrl_dvi_odf;
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input [ 1: 0] ctrl_cd;
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input ctrl_pc;
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input [31: 0] fb_data_fifo_q;
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input fb_data_fifo_empty;
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output fb_data_fifo_rreq;
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input ImDoneFifoQ;
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output stat_acmp; // active CLUT memory page
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reg stat_acmp;
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output clut_req;
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output [ 8: 0] clut_adr;
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input [23: 0] clut_q;
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input clut_ack;
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input ctrl_cbsw; // enable clut bank switching
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output clut_switch; // clut memory bank-switch request: clut page switched (when enabled)
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input [ 8: 0] cursor_adr; // cursor data address (from wbm)
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input cursor0_en; // enable hardware cursor0
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input cursor0_res; // cursor0 resolution
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input [31: 0] cursor0_xy; // (x,y) address hardware cursor0
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output [ 3: 0] cc0_adr_o; // cursor0 color registers address output
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input [15: 0] cc0_dat_i; // cursor0 color registers data input
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input cursor1_en; // enable hardware cursor1
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input cursor1_res; // cursor1 resolution
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input [31: 0] cursor1_xy; // (x,y) address hardware cursor1
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output [ 3: 0] cc1_adr_o; // cursor1 color registers address output
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input [15: 0] cc1_dat_i; // cursor1 color registers data input
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input line_fifo_full;
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output line_fifo_wreq;
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output [23: 0] line_fifo_d;
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output line_fifo_rreq;
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input [23: 0] line_fifo_q;
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// pixel clock related outputs
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input pclk_i; // pixel clock in
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output pclk_o; // pixel clock out
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output hsync_o; // horizontal sync pulse
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output vsync_o; // vertical sync pulse
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output csync_o; // composite sync: Hsync OR Vsync (logical OR function)
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output blank_o; // blanking signal
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output [ 7:0] r_o, g_o, b_o;
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reg hsync_o, vsync_o, csync_o, blank_o;
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reg [7:0] r_o, g_o, b_o;
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`ifdef VGA_12BIT_DVI
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output dvi_pclk_p_o; // dvi pclk+
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output dvi_pclk_m_o; // dvi pclk-
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output dvi_hsync_o; // dvi hsync
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output dvi_vsync_o; // dvi vsync
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output dvi_de_o; // dvi data enable
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output [11:0] dvi_d_o; // dvi 12bit output
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`endif
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//
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// variable declarations
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//
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reg nVen; // video enable signal (active low)
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wire eol, eof;
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wire ihsync, ivsync, icsync, iblank;
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wire pclk_ena;
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//////////////////////////////////
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//
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// module body
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//
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// synchronize timing/control settings (from master-clock-domain to pixel-clock-domain)
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always @(posedge pclk_i)
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nVen <= #1 ~ctrl_ven;
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//////////////////////////////////
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//
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// Pixel Clock generator
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//
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vga_clkgen clk_gen(
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.pclk_i ( pclk_i ),
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.rst_i ( nVen ),
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.pclk_o ( pclk_o ),
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.dvi_pclk_p_o ( dvi_pclk_p_o ),
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.dvi_pclk_m_o ( dvi_pclk_m_o ),
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.pclk_ena_o ( pclk_ena )
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);
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//////////////////////////////////
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//
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// Timing generator
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//
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// hookup video timing generator
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vga_tgen vtgen(
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.clk(pclk_i),
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.clk_ena ( pclk_ena ),
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.rst ( nVen ),
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.Thsync ( Thsync ),
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.Thgdel ( Thgdel ),
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.Thgate ( Thgate ),
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.Thlen ( Thlen ),
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.Tvsync ( Tvsync ),
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.Tvgdel ( Tvgdel ),
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.Tvgate ( Tvgate ),
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.Tvlen ( Tvlen ),
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.eol ( eol ),
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.eof ( eof ),
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.gate ( gate ),
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.hsync ( ihsync ),
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.vsync ( ivsync ),
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.csync ( icsync ),
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.blank ( iblank )
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);
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//
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// from pixel-clock-domain to master-clock-domain
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//
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reg seol, seof; // synchronized end-of-line, end-of-frame
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reg dseol, dseof; // delayed seol, seof
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always @(posedge clk_i)
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if (~ctrl_ven)
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begin
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seol <= #1 1'b0;
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dseol <= #1 1'b0;
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seof <= #1 1'b0;
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dseof <= #1 1'b0;
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eoh <= #1 1'b0;
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eov <= #1 1'b0;
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end
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else
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begin
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seol <= #1 eol;
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dseol <= #1 seol;
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seof <= #1 eof;
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dseof <= #1 seof;
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eoh <= #1 seol & !dseol;
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eov <= #1 seof & !dseof;
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end
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`ifdef VGA_12BIT_DVI
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always @(posedge pclk_i)
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if (pclk_ena)
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begin
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hsync_o <= #1 ihsync ^ ctrl_HSyncL;
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vsync_o <= #1 ivsync ^ ctrl_VSyncL;
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csync_o <= #1 icsync ^ ctrl_CSyncL;
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blank_o <= #1 iblank ^ ctrl_BlankL;
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end
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`else
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reg hsync, vsync, csync, blank;
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always @(posedge pclk_i)
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begin
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hsync <= #1 ihsync ^ ctrl_HSyncL;
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vsync <= #1 ivsync ^ ctrl_VSyncL;
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csync <= #1 icsync ^ ctrl_CSyncL;
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blank <= #1 iblank ^ ctrl_BlankL;
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hsync_o <= #1 hsync;
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vsync_o <= #1 vsync;
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csync_o <= #1 csync;
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blank_o <= #1 blank;
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end
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`endif
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//////////////////////////////////
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//
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// Pixel generator section
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//
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wire [23:0] color_proc_q; // data from color processor
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wire color_proc_wreq;
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wire [ 7:0] clut_offs; // color lookup table offset
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wire ImDoneFifoQ;
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reg dImDoneFifoQ, ddImDoneFifoQ;
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wire [23:0] cur1_q;
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wire cur1_wreq;
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wire [23:0] rgb_fifo_d;
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wire rgb_fifo_empty, rgb_fifo_full, rgb_fifo_rreq, rgb_fifo_wreq;
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wire sclr = ~ctrl_ven;
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//
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// hookup color processor
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vga_colproc color_proc (
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.clk ( clk_i ),
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.srst ( sclr ),
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.vdat_buffer_di ( fb_data_fifo_q ), //data_fifo_q),
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.ColorDepth ( ctrl_cd ),
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.PseudoColor ( ctrl_pc ),
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.vdat_buffer_empty ( fb_data_fifo_empty ), //data_fifo_empty),
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.vdat_buffer_rreq ( fb_data_fifo_rreq ), //data_fifo_rreq),
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.rgb_fifo_full ( rgb_fifo_full ),
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.rgb_fifo_wreq ( color_proc_wreq ),
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.r ( color_proc_q[23:16] ),
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.g ( color_proc_q[15: 8] ),
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.b ( color_proc_q[ 7: 0] ),
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.clut_req ( clut_req ),
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.clut_ack ( clut_ack ),
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.clut_offs ( clut_offs ),
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.clut_q ( clut_q )
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);
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//
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// clut bank switch / cursor data delay2: Account for ColorProcessor DataBuffer delay
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always @(posedge clk_i)
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if (sclr)
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dImDoneFifoQ <= #1 1'b0;
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else if (fb_data_fifo_rreq)
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dImDoneFifoQ <= #1 ImDoneFifoQ;
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always @(posedge clk_i)
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if (sclr)
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ddImDoneFifoQ <= #1 1'b0;
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else
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ddImDoneFifoQ <= #1 dImDoneFifoQ;
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assign clut_switch = ddImDoneFifoQ & !dImDoneFifoQ;
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always @(posedge clk_i)
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if (sclr)
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stat_acmp <= #1 1'b0;
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else if (ctrl_cbsw)
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stat_acmp <= #1 stat_acmp ^ clut_switch; // select next clut when finished reading clut for current video bank (and bank switch enabled)
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// generate clut-address
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assign clut_adr = {stat_acmp, clut_offs};
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//
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// hookup data-source-selector && hardware cursor module
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`ifdef VGA_HWC1 // generate Hardware Cursor1 (if enabled)
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wire cursor1_ld_strb;
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reg scursor1_en;
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reg scursor1_res;
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reg [31:0] scursor1_xy;
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assign cursor1_ld_strb = ddImDoneFifoQ & !dImDoneFifoQ;
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always @(posedge clk_i)
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if (sclr)
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scursor1_en <= #1 1'b0;
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else if (cursor1_ld_strb)
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scursor1_en <= #1 cursor1_en;
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always @(posedge clk_i)
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if (cursor1_ld_strb)
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scursor1_xy <= #1 cursor1_xy;
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always @(posedge clk_i)
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if (cursor1_ld_strb)
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scursor1_res <= #1 cursor1_res;
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vga_curproc hw_cursor1 (
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.clk ( clk_i ),
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.rst_i ( sclr ),
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.Thgate ( Thgate ),
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.Tvgate ( Tvgate ),
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.idat ( color_proc_q ),
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.idat_wreq ( color_proc_wreq ),
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.cursor_xy ( scursor1_xy ),
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.cursor_res ( scursor1_res ),
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.cursor_en ( scursor1_en ),
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.cursor_wadr ( cursor_adr ),
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.cursor_we ( cursor1_we ),
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.cursor_wdat ( dat_i ),
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.cc_adr_o ( cc1_adr_o ),
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.cc_dat_i ( cc1_dat_i ),
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.rgb_fifo_wreq ( cur1_wreq ),
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.rgb ( cur1_q )
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);
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`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled)
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reg sddImDoneFifoQ, sdImDoneFifoQ;
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always @(posedge clk_i)
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if (cur1_wreq)
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begin
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sdImDoneFifoQ <= #1 dImDoneFifoQ;
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sddImDoneFifoQ <= #1 sdImDoneFifoQ;
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end
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`endif
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`else // Hardware Cursor1 disabled, generate pass-through signals
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assign cur1_wreq = color_proc_wreq;
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assign cur1_q = color_proc_q;
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assign cc1_adr_o = 4'h0;
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`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled)
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wire sddImDoneFifoQ, sdImDoneFifoQ;
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assign sdImDoneFifoQ = dImDoneFifoQ;
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assign sddImDoneFifoQ = ddImDoneFifoQ;
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`endif
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`endif
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`ifdef VGA_HWC0 // generate Hardware Cursor0 (if enabled)
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wire cursor0_ld_strb;
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reg scursor0_en;
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reg scursor0_res;
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reg [31:0] scursor0_xy;
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assign cursor0_ld_strb = sddImDoneFifoQ & !sdImDoneFifoQ;
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always @(posedge clk_i)
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if (sclr)
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scursor0_en <= #1 1'b0;
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else if (cursor0_ld_strb)
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scursor0_en <= #1 cursor0_en;
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always @(posedge clk_i)
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if (cursor0_ld_strb)
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scursor0_xy <= #1 cursor0_xy;
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always @(posedge clk_i)
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if (cursor0_ld_strb)
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scursor0_res <= #1 cursor0_res;
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vga_curproc hw_cursor0 (
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.clk ( clk_i ),
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.rst_i ( sclr ),
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.Thgate ( Thgate ),
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.Tvgate ( Tvgate ),
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.idat ( ssel1_q ),
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.idat_wreq ( ssel1_wreq ),
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.cursor_xy ( scursor0_xy ),
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.cursor_en ( scursor0_en ),
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.cursor_res ( scursor0_res ),
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.cursor_wadr ( cursor_adr ),
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.cursor_we ( cursor0_we ),
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.cursor_wdat ( dat_i ),
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.cc_adr_o ( cc0_adr_o ),
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.cc_dat_i ( cc0_dat_i ),
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.rgb_fifo_wreq ( rgb_fifo_wreq ),
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.rgb ( rgb_fifo_d )
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);
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`else // Hardware Cursor0 disabled, generate pass-through signals
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assign rgb_fifo_wreq = cur1_wreq;
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assign rgb_fifo_d = cur1_q;
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assign cc0_adr_o = 4'h0;
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`endif
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//
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// hookup RGB buffer (temporary station between WISHBONE-clock-domain
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// and pixel-clock-domain)
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// The cursor_processor pipelines introduce a delay between the color
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// processor's rgb_fifo_wreq and the rgb_fifo_full signals. To compensate
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// for this we double the rgb_fifo.
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wire [4:0] rgb_fifo_nword;
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|
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vga_fifo #(4, 24) rgb_fifo (
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.clk ( clk_i ),
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.aclr ( 1'b1 ),
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.sclr ( sclr ),
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.d ( rgb_fifo_d ),
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.wreq ( rgb_fifo_wreq ),
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.q ( line_fifo_d ),
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.rreq ( rgb_fifo_rreq ),
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.empty ( rgb_fifo_empty ),
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.nword ( rgb_fifo_nword ),
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|
.full ( ),
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|
.aempty ( ),
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|
.afull ( )
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|
);
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|
|
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assign rgb_fifo_full = rgb_fifo_nword[3]; // actually half full
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|
|
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assign line_fifo_rreq = gate & pclk_ena;
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|
|
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assign rgb_fifo_rreq = ~line_fifo_full & ~rgb_fifo_empty;
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assign line_fifo_wreq = rgb_fifo_rreq;
|
|
|
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wire [7:0] r = line_fifo_q[23:16];
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|
wire [7:0] g = line_fifo_q[15: 8];
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|
wire [7:0] b = line_fifo_q[ 7: 0];
|
|
|
|
always @(posedge pclk_i)
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|
if (pclk_ena) begin
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|
r_o <= #1 r;
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|
g_o <= #1 g;
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|
b_o <= #1 b;
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|
end
|
|
|
|
|
|
//
|
|
// DVI section
|
|
//
|
|
|
|
`ifdef VGA_12BIT_DVI
|
|
reg [11:0] dvi_d_o;
|
|
reg dvi_de_o;
|
|
reg dvi_hsync_o;
|
|
reg dvi_vsync_o;
|
|
|
|
reg [11:0] pA, pB;
|
|
reg dgate, ddgate;
|
|
reg dhsync, ddhsync;
|
|
reg dvsync, ddvsync;
|
|
|
|
always @(posedge pclk_i)
|
|
if (pclk_ena)
|
|
case (ctrl_dvi_odf) // synopsys full_case parallel_case
|
|
2'b00: pA <= #1 {g[3:0], b[7:0]};
|
|
2'b01: pA <= #1 {g[4:2], b[7:3], g[0], b[2:0]};
|
|
2'b10: pA <= #1 {g[4:2], b[7:3], 4'h0};
|
|
2'b11: pA <= #1 {g[5:3], b[7:3], 4'h0};
|
|
endcase
|
|
|
|
always @(posedge pclk_i)
|
|
if (pclk_ena)
|
|
case (ctrl_dvi_odf) // synopsys full_case parallel_case
|
|
2'b00: pB <= #1 {r[7:0], g[7:4]};
|
|
2'b01: pB <= #1 {r[7:3], g[7:5], r[2:0], g[1]};
|
|
2'b10: pB <= #1 {r[7:3], g[7:5], 4'h0};
|
|
2'b11: pB <= #1 {1'b0, r[7:3], g[7:6], 4'h0};
|
|
endcase
|
|
|
|
always @(posedge pclk_i)
|
|
if (pclk_ena)
|
|
dvi_d_o <= #1 pB;
|
|
else
|
|
dvi_d_o <= #1 pA;
|
|
|
|
always @(posedge pclk_i)
|
|
if (pclk_ena) begin
|
|
dgate <= #1 gate; // delay once: delayed line fifo output
|
|
|
|
dhsync <= #1 ~ihsync;
|
|
ddhsync <= #1 dhsync;
|
|
|
|
dvsync <= #1 ~ivsync;
|
|
ddvsync <= #1 dvsync;
|
|
end
|
|
|
|
always @(posedge pclk_i)
|
|
begin
|
|
dvi_de_o <= #1 dgate;
|
|
dvi_hsync_o <= #1 dhsync;
|
|
dvi_vsync_o <= #1 dvsync;
|
|
end
|
|
|
|
`endif
|
|
|
|
endmodule
|
|
|