511 lines
13 KiB
Verilog
511 lines
13 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant VGA/LCD Core ////
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//// Enhanced Color Processor ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/vga_lcd ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001, 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: vga_colproc.v,v 1.8 2003/05/07 09:48:54 rherveille Exp $
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//
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// $Date: 2003/05/07 09:48:54 $
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// $Revision: 1.8 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: vga_colproc.v,v $
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// Revision 1.8 2003/05/07 09:48:54 rherveille
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// Fixed some Wishbone RevB.3 related bugs.
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// Changed layout of the core. Blocks are located more logically now.
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// Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.
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//
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// Revision 1.7 2002/03/04 11:01:59 rherveille
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// Added 64x64pixels 4bpp hardware cursor support.
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//
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// Revision 1.6 2002/02/07 05:42:10 rherveille
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// Fixed some bugs discovered by modified testbench
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// Removed / Changed some strange logic constructions
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// Started work on hardware cursor support (not finished yet)
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// Changed top-level name to vga_enh_top.v
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//
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//synopsys translate_off
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`include "timescale.v"
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//synopsys translate_on
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module vga_colproc(clk, srst, vdat_buffer_di, ColorDepth, PseudoColor,
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vdat_buffer_empty, vdat_buffer_rreq, rgb_fifo_full,
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rgb_fifo_wreq, r, g, b,
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clut_req, clut_ack, clut_offs, clut_q
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);
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//
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// inputs & outputs
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//
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input clk; // master clock
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input srst; // synchronous reset
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input [31:0] vdat_buffer_di; // video memory data input
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input [1:0] ColorDepth; // color depth (8bpp, 16bpp, 24bpp)
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input PseudoColor; // pseudo color enabled (only for 8bpp color depth)
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input vdat_buffer_empty;
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output vdat_buffer_rreq; // pixel buffer read request
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reg vdat_buffer_rreq;
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input rgb_fifo_full;
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output rgb_fifo_wreq;
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reg rgb_fifo_wreq;
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output [7:0] r, g, b; // pixel color information
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reg [7:0] r, g, b;
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output clut_req; // clut request
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reg clut_req;
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input clut_ack; // clut acknowledge
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output [ 7:0] clut_offs; // clut offset
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reg [7:0] clut_offs;
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input [23:0] clut_q; // clut data in
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//
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// variable declarations
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//
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reg [31:0] DataBuffer;
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reg [7:0] Ra, Ga, Ba;
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reg [1:0] colcnt;
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reg RGBbuf_wreq;
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//
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// Module body
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//
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// store word from pixelbuffer / wishbone input
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always @(posedge clk)
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if (vdat_buffer_rreq)
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DataBuffer <= #1 vdat_buffer_di;
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//
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// generate statemachine
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//
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// extract color information from data buffer
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parameter idle = 7'b000_0000,
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fill_buf = 7'b000_0001,
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bw_8bpp = 7'b000_0010,
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col_8bpp = 7'b000_0100,
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col_16bpp_a = 7'b000_1000,
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col_16bpp_b = 7'b001_0000,
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col_24bpp = 7'b010_0000,
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col_32bpp = 7'b100_0000;
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reg [6:0] c_state; // xsynopsys enum_state
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reg [6:0] nxt_state; // xsynopsys enum_state
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// next state decoder
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always @(c_state or vdat_buffer_empty or ColorDepth or PseudoColor or rgb_fifo_full or colcnt or clut_ack)
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begin : nxt_state_decoder
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// initial value
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nxt_state = c_state;
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case (c_state) // synopsis full_case parallel_case
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// idle state
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idle:
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if (!vdat_buffer_empty && !rgb_fifo_full)
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nxt_state = fill_buf;
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// fill data buffer
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fill_buf:
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case (ColorDepth) // synopsis full_case parallel_case
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2'b00:
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if (PseudoColor)
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nxt_state = col_8bpp;
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else
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nxt_state = bw_8bpp;
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2'b01:
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nxt_state = col_16bpp_a;
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2'b10:
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nxt_state = col_24bpp;
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2'b11:
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nxt_state = col_32bpp;
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endcase
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//
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// 8 bits per pixel
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//
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bw_8bpp:
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if (!rgb_fifo_full && !(|colcnt) )
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if (!vdat_buffer_empty)
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nxt_state = fill_buf;
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else
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nxt_state = idle;
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col_8bpp:
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// Do NOT check for rgb_fifo_full here.
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// In 8bpp pseudo-color mode the color-processor must always finish
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// the current 4pixel-block(i.e. it runs until colcnt = '11').
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// This is because of the late clut-response which shuffles all
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// signals the state-machine depends on.
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// Because of this we can not do an early video_memory_data fetch,
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// i.e. we can not jump to the fill_buf state. Instead we always
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// jump to idle and check for rgb_fifo_full there.
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//
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// The addition of the cursor-processors forces us to increase the
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// rgb-fifo size. The increased rgb-fifo also handles the above
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// described problem. Thus erradicating the above comment.
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// We add the early video_memory_data fetch again.
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if (!(|colcnt))
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if (!vdat_buffer_empty && !rgb_fifo_full)
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nxt_state = fill_buf;
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else
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nxt_state = idle;
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//
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// 16 bits per pixel
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//
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col_16bpp_a:
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if (!rgb_fifo_full)
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nxt_state = col_16bpp_b;
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col_16bpp_b:
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if (!rgb_fifo_full)
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if (!vdat_buffer_empty)
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nxt_state = fill_buf;
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else
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nxt_state = idle;
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//
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// 24 bits per pixel
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//
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col_24bpp:
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if (!rgb_fifo_full)
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if (colcnt == 2'h1) // (colcnt == 1)
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nxt_state = col_24bpp; // stay in current state
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else if (!vdat_buffer_empty)
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nxt_state = fill_buf;
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else
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nxt_state = idle;
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//
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// 32 bits per pixel
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//
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col_32bpp:
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if (!rgb_fifo_full)
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if (!vdat_buffer_empty)
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nxt_state = fill_buf;
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else
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nxt_state = idle;
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endcase
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end // next state decoder
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// generate state registers
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always @(posedge clk)
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if (srst)
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c_state <= #1 idle;
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else
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c_state <= #1 nxt_state;
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reg iclut_req;
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reg ivdat_buf_rreq;
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reg [7:0] iR, iG, iB, iRa, iGa, iBa;
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// output decoder
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always @(c_state or vdat_buffer_empty or colcnt or DataBuffer or rgb_fifo_full or clut_ack or clut_q or Ba or Ga or Ra)
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begin : output_decoder
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// initial values
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ivdat_buf_rreq = 1'b0;
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RGBbuf_wreq = 1'b0;
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iclut_req = 1'b0;
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iR = 'h0;
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iG = 'h0;
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iB = 'h0;
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iRa = 'h0;
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iGa = 'h0;
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iBa = 'h0;
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case (c_state) // synopsis full_case parallel_case
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idle:
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begin
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if (!rgb_fifo_full)
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if (!vdat_buffer_empty)
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ivdat_buf_rreq = 1'b1;
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// when entering from 8bpp_pseudo_color_mode
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RGBbuf_wreq = clut_ack;
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iR = clut_q[23:16];
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iG = clut_q[15: 8];
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iB = clut_q[ 7: 0];
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end
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fill_buf:
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begin
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// when entering from 8bpp_pseudo_color_mode
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RGBbuf_wreq = clut_ack;
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iR = clut_q[23:16];
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iG = clut_q[15: 8];
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iB = clut_q[ 7: 0];
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end
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//
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// 8 bits per pixel
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//
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bw_8bpp:
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begin
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if (!rgb_fifo_full)
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begin
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RGBbuf_wreq = 1'b1;
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if ( (!vdat_buffer_empty) && !(|colcnt) )
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ivdat_buf_rreq = 1'b1;
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end
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case (colcnt) // synopsis full_case parallel_case
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2'b11:
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begin
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iR = DataBuffer[31:24];
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iG = DataBuffer[31:24];
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iB = DataBuffer[31:24];
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end
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2'b10:
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begin
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iR = DataBuffer[23:16];
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iG = DataBuffer[23:16];
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iB = DataBuffer[23:16];
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end
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2'b01:
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begin
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iR = DataBuffer[15:8];
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iG = DataBuffer[15:8];
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iB = DataBuffer[15:8];
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end
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default:
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begin
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iR = DataBuffer[7:0];
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iG = DataBuffer[7:0];
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iB = DataBuffer[7:0];
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end
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endcase
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end
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col_8bpp:
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begin
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// Do NOT check for rgb_fifo_full here.
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// In 8bpp pseudo-color mode the color-processor must always finish
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// the current 4pixel-block(i.e. it runs until colcnt = '11').
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// This is because of the late clut-response which shuffles all
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// signals the state-machine depends on.
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// Because of this we can not do an early video_memory_data fetch,
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// i.e. we can not jump to the fill_buf state. Instead we always
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// jump to idle and check for rgb_fifo_full there.
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//
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// The addition of the cursor-processors forces us to increase the
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// rgb-fifo size. The increased rgb-fifo also handles the above
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// described problem. Thus erradicating the above comment.
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// We add the early video_memory_data fetch again.
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if (!(|colcnt))
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if (!vdat_buffer_empty && !rgb_fifo_full)
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ivdat_buf_rreq = 1'b1;
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RGBbuf_wreq = clut_ack;
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iR = clut_q[23:16];
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iG = clut_q[15: 8];
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iB = clut_q[ 7: 0];
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iclut_req = !rgb_fifo_full || (colcnt[1] ^ colcnt[0]);
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end
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//
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// 16 bits per pixel
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//
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col_16bpp_a:
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begin
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if (!rgb_fifo_full)
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RGBbuf_wreq = 1'b1;
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iR[7:3] = DataBuffer[31:27];
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iG[7:2] = DataBuffer[26:21];
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iB[7:3] = DataBuffer[20:16];
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end
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col_16bpp_b:
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begin
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if (!rgb_fifo_full)
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begin
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RGBbuf_wreq = 1'b1;
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if (!vdat_buffer_empty)
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ivdat_buf_rreq = 1'b1;
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end
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iR[7:3] = DataBuffer[15:11];
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iG[7:2] = DataBuffer[10: 5];
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iB[7:3] = DataBuffer[ 4: 0];
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end
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//
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// 24 bits per pixel
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//
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col_24bpp:
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begin
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if (!rgb_fifo_full)
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begin
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RGBbuf_wreq = 1'b1;
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if ( (colcnt != 2'h1) && !vdat_buffer_empty)
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ivdat_buf_rreq = 1'b1;
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end
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case (colcnt) // synopsis full_case parallel_case
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2'b11:
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begin
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iR = DataBuffer[31:24];
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iG = DataBuffer[23:16];
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iB = DataBuffer[15: 8];
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iRa = DataBuffer[ 7: 0];
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end
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2'b10:
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begin
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iR = Ra;
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iG = DataBuffer[31:24];
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iB = DataBuffer[23:16];
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iRa = DataBuffer[15: 8];
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iGa = DataBuffer[ 7: 0];
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end
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2'b01:
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begin
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iR = Ra;
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iG = Ga;
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iB = DataBuffer[31:24];
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iRa = DataBuffer[23:16];
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iGa = DataBuffer[15: 8];
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iBa = DataBuffer[ 7: 0];
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end
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default:
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begin
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iR = Ra;
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iG = Ga;
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iB = Ba;
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end
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endcase
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end
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//
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// 32 bits per pixel
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//
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col_32bpp:
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begin
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if (!rgb_fifo_full)
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begin
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RGBbuf_wreq = 1'b1;
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if (!vdat_buffer_empty)
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ivdat_buf_rreq = 1'b1;
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end
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iR[7:0] = DataBuffer[23:16];
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iG[7:0] = DataBuffer[15:8];
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iB[7:0] = DataBuffer[7:0];
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end
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endcase
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end // output decoder
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// generate output registers
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always @(posedge clk)
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begin
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r <= #1 iR;
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g <= #1 iG;
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b <= #1 iB;
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if (RGBbuf_wreq)
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begin
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Ra <= #1 iRa;
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Ba <= #1 iBa;
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Ga <= #1 iGa;
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end
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if (srst)
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begin
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vdat_buffer_rreq <= #1 1'b0;
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rgb_fifo_wreq <= #1 1'b0;
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clut_req <= #1 1'b0;
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end
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else
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begin
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vdat_buffer_rreq <= #1 ivdat_buf_rreq;
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rgb_fifo_wreq <= #1 RGBbuf_wreq;
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clut_req <= #1 iclut_req;
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end
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end
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// assign clut offset
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always @(colcnt or DataBuffer)
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case (colcnt) // synopsis full_case parallel_case
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2'b11: clut_offs = DataBuffer[31:24];
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2'b10: clut_offs = DataBuffer[23:16];
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2'b01: clut_offs = DataBuffer[15: 8];
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2'b00: clut_offs = DataBuffer[ 7: 0];
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endcase
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//
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// color counter
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//
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always @(posedge clk)
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if (srst)
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colcnt <= #1 2'b11;
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else if (RGBbuf_wreq)
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colcnt <= #1 colcnt -2'h1;
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endmodule
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